We are using Cortex-M0 DesignStart Pro to design MCU. When we use SWD to download grogram to flash in FPGA(Cortex_m0 mcu inside), we cannot to connect keil with FPGA, and Keil shows:" Could not stop Cortex-M device!Please check the JTAG cable. "
Attached are keil display error messages, simulation waveforms, and data analysis captured by the logic analyzer.
Yes, I am using DesignStart pro (full RTL) , so I don't need to set DesignStart pro (full RTL) , but must set CORTEX_M0 in my synthesis， and no need to set for simulation , is it?
I have setup clock constraints for SWCLKTCK in my synthesis constraints.