We are using Cortex-M0 DesignStart Pro to design MCU. When we use SWD to download grogram to flash in FPGA(Cortex_m0 mcu inside), we cannot to connect keil with FPGA, and Keil shows:" Could not stop Cortex-M device!Please check the JTAG cable. "
Attached are keil display error messages, simulation waveforms, and data analysis captured by the logic analyzer.
Have you hook up SYSRESETREQ from the processor to reset the system? (please make sure this should not reset debug logic, i.e. not use as power on reset).
In the Keil project, please also remove flash programming in debug option.
I don't Know how to hook up SYSRESETREQ from the processor to reset the system.Whether in SWDIOTMS input or normal run FLASH program, I see that SYSRESETREQ has been low level, do not know how to use. Could you help to tell me how to use hook up SYSRESETREQ from the processor to reset the system, or Or give me some information to study?
For Cortex-M0 design start:
The RTL simulation environment possibly doesn't use the SYSRESETREQ feature. It is used by real debugger to reset the processor, which happen during the debug connection sequence.
If you are using design start, you can possibly see the following modules:
Here you can see
// System Reset request can be from processor or watchdog // or when lockup happens and the control flag is set. assign cmsdk_SYSRESETREQ = SYSRESETREQ | WDOGRESETREQ | (LOCKUP & LOCKUPRESET);
// CPU request or watchdog request (SYSRESETREQ) assign clk_ctrl_sys_reset_req = PMUHRESETREQ | cmsdk_SYSRESETREQ;
This module generates the actual HRESETn signal.
Yes, I have seen these, and I don't change these code, but still failed! And I see it must define CORTEX_M0DESIGNSTART in RTL, and in cmsdk_mcu_defs.v , it shows:
The system level RTL has a number condition compile codes like
This is needed as designstart eval possibly has different top level pins compared to full RTL.
If you are using DesignStart pro (full RTL) you don't need to set this macro.
I think you should set CORTEX_M0 in your synthesis.
Another thing to check is whether you have setup clock constraints for SWCLKTCK (missing clock contraints can also cause problem.).
Yes, I am using DesignStart pro (full RTL) , so I don't need to set DesignStart pro (full RTL) , but must set CORTEX_M0 in my synthesis， and no need to set for simulation , is it?
I have setup clock constraints for SWCLKTCK in my synthesis constraints.
If I set this macro in simulation and synthesis , is ok, right?
Yes, you need to set CORTEX_M0 in your synthesis.
You can set it in both simulation and synthesis environment.
Could you also check your Keil MDK project debug option - in debug probe setting, there might be choices of reset types: It should be SYSRESETREQ
I have set these macro , and re-synthesis.
And then choice of reset types: SYSRESETREQ.
But it failed again, and the info as follows:
This is not a failure message - this is expected because the flash programming option is removed in the debug option (you don't have flash memory in your FPGA).
I see, but I use RAM to equate FLASH memory. Can I download hex into RAM? Can I debug the gpogram used SWD? What should we do with KEIL in order to download programs to RAM? What should we do with SOC in order to download programs to Flash memory(RAM in FPGA)?
Yes, you can download program image to an SRAM location and execute and debug it using SWD.
By the way, which FPGA board are you using? And which debug probe? (ULINK? I-Jet?)
My FPGA borad is Xilinx's XC7Z020, debug probe is ST-LINK V2.
I am not sure if you can use ST-LINK to program non ST devices. In the past I saw some forum posts said that the probe is locked down to ST device only
You might need to get a different debug adapter for your FPGA project.
OK, I see， which debug probe that you recommend?