DesignStart Eval : The number of INTISR in Cortex-M3

Cortex-M3 softcore minimal SoC

'xilinx.com:ip:axi_bram_ctrl:4.0' does not support the current part 'xc7a35ticsg324-1L'

Design Start standard cell libraries have DRC errors in 45 RF SOI?

ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD cell