Arm Community
Site
Search
User
Site
Search
User
Groups
Arm Research
DesignStart
Education Hub
Graphics and Gaming
High Performance Computing
Innovation
Multimedia
Open Source Software and Platforms
Physical
Processors
Security
System
Software Tools
TrustZone for Armv8-M
中文社区
Blog
Announcements
Artificial Intelligence
Automotive
Healthcare
HPC
Infrastructure
Innovation
Internet of Things
Machine Learning
Mobile
Smart Homes
Wearables
Forums
All developer forums
IP Product forums
Tool & Software forums
Support
Open a support case
Documentation
Downloads
Training
Arm Approved program
Arm Design Reviews
Community Help
More
Cancel
Developer Community
IP Products
Processors
DesignStart
Jump...
Cancel
DesignStart
Blog
Forum
Videos & Files
Jump...
Cancel
New
DesignStart requires membership for participation - click to join
More developer forums
Android forum
Arm Compilers forum
Arm Development Platforms forum
Arm Development Studio forum
Classic processors forum
Cortex-A / A-Profile forum
Cortex-M / M-Profile forum
Cortex-R / R-Profile forum
Embedded forum
GNU Toolchain forum
Graphics and Gaming forum
HPC forum
Infrastructure Solutions
Keil forum
Machine Learning forum
Morello Forum
Simulation Models forum
SoC Design forum
Related tags
ACE
AXI
CHI
Cortex-M
Cortex-M Prototyping System (V2M-MPS2)
Cortex-M0
Cortex-M1
Cortex-M3
Custom SoC
DesignStart
FPGA
Keil
MPI
Simulation
Verilog
Forums
DesignStart forum
Discussion about custom SoC design with Arm IP through the easy-access DesignStart program.
168
questions
Porting AT472-BU-98000-r0p1-00rel0 to Avnet 7a50t development board failed
1 month ago
All questions in this Community
By title
By date
By reply count
By view count
By most asked
By votes
By quality
Descending
Ascending
All recent questions and discussions
Unread questions and discussions
Questions and discussions you've participated in
Questions and discussions you've started
Unanswered questions and discussions
Answered questions and discussions
Questions with suggested answers
Questions and discussions with no replies
Not Answered
Porting AT472-BU-98000-r0p1-00rel0 to Avnet 7a50t development board failed
0
158
views
0
replies
Started
1 month ago
by
x_gate
Answered
Simulate Cortex-M0 FPGA implementation in ModelSim
+1
Verilog
Cortex-M0
FPGA
CHI
Compiling
DesignStart
MPI
Cortex-M
Windows
Linux
2560
views
2
replies
Latest
1 month ago
by
JamesBr
Not Answered
How to send the encoder/ pulses over serial port of 8051
0
385
views
0
replies
Started
3 months ago
by
Vignesh vsg
Not Answered
m1/m3 design start download problems
0
714
views
2
replies
Latest
4 months ago
by
ChrisR
Answered
Zephyr RTOS support for Cortex-M1 reference design is here
0
Real Time Operating Systems (RTOS)
FPGA
789
views
1
reply
Latest
5 months ago
by
Brix
Suggested Answer
SWD: Cannot connect to MEM-AP on Cortex-M0 Designstart Eval
0
Cortex-M0
DesignStart
SWD
969
views
4
replies
Latest
5 months ago
by
Bernhard Lang
Answered
V2C-DAPLINK-035A shield schematic
0
FPGA
Debug Adapters
748
views
1
reply
Latest
6 months ago
by
Sean Houlihane
Not Answered
MPS3 HDMI Output
0
699
views
0
replies
Started
6 months ago
by
davemap
Suggested Answer
DesignStart Eval : The number of INTISR in Cortex-M3
0
617
views
1
reply
Latest
6 months ago
by
Mahmood Yakub
Answered
Does the DesignStart FPGA Cortex-M1/M3 support SWD multi-drop?
0
FPGA
SWD
702
views
1
reply
Latest
6 months ago
by
Mahmood Yakub
Not Answered
Cortex-M3 softcore minimal SoC
0
Cortex-M3
DesignStart
822
views
0
replies
Started
8 months ago
by
TinyLabs
Suggested Answer
'xilinx.com:ip:axi_bram_ctrl:4.0' does not support the current part 'xc7a35ticsg324-1L'
0
AXI
DesignStart
Support
Block
5939
views
5
replies
Latest
8 months ago
by
Ahmed Benabdallah
Not Answered
Design Start standard cell libraries have DRC errors in 45 RF SOI?
0
550
views
0
replies
Started
8 months ago
by
Travis6
Answered
ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD cell
0
3396
views
3
replies
Latest
9 months ago
by
jpthibault
Not Answered
what is the extra FPGA utilization of debug/trace features in Cortex-M3 Xilinx edition
0
528
views
0
replies
Started
9 months ago
by
yonathan
>