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DesignStart forum
Discussion about custom SoC design with Arm IP through the easy-access DesignStart program.
167
questions
How to send the encoder/ pulses over serial port of 8051
2 days ago
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Not Answered
How to send the encoder/ pulses over serial port of 8051
0
108
views
0
replies
Started
2 days ago
by
Vignesh vsg
Not Answered
m1/m3 design start download problems
0
284
views
2
replies
Latest
1 month ago
by
ChrisR
Answered
Zephyr RTOS support for Cortex-M1 reference design is here
0
Real Time Operating Systems (RTOS)
FPGA
490
views
1
reply
Latest
2 months ago
by
Brix
Suggested Answer
SWD: Cannot connect to MEM-AP on Cortex-M0 Designstart Eval
0
Cortex-M0
DesignStart
SWD
623
views
4
replies
Latest
2 months ago
by
Bernhard Lang
Answered
V2C-DAPLINK-035A shield schematic
0
FPGA
Debug Adapters
496
views
1
reply
Latest
3 months ago
by
Sean Houlihane
Not Answered
MPS3 HDMI Output
0
493
views
0
replies
Started
3 months ago
by
davemap
Suggested Answer
DesignStart Eval : The number of INTISR in Cortex-M3
0
438
views
1
reply
Latest
3 months ago
by
Mahmood Yakub
Answered
Does the DesignStart FPGA Cortex-M1/M3 support SWD multi-drop?
0
FPGA
SWD
453
views
1
reply
Latest
3 months ago
by
Mahmood Yakub
Not Answered
Cortex-M3 softcore minimal SoC
0
Cortex-M3
DesignStart
639
views
0
replies
Started
5 months ago
by
TinyLabs
Suggested Answer
'xilinx.com:ip:axi_bram_ctrl:4.0' does not support the current part 'xc7a35ticsg324-1L'
0
AXI
DesignStart
Support
Block
5209
views
5
replies
Latest
5 months ago
by
Ahmed Benabdallah
Not Answered
Design Start standard cell libraries have DRC errors in 45 RF SOI?
0
359
views
0
replies
Started
6 months ago
by
Travis6
Answered
ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD cell
0
2885
views
3
replies
Latest
6 months ago
by
jpthibault
Not Answered
what is the extra FPGA utilization of debug/trace features in Cortex-M3 Xilinx edition
0
338
views
0
replies
Started
6 months ago
by
yonathan
Not Answered
Is it possible to run a cycle mode (i,e DSM=yes) for CORTEX-M0 processor?
0
461
views
0
replies
Started
6 months ago
by
Rocker_Hacker
Not Answered
Is it possible to run a cycle mode (i,e DSM=yes) for CORTEX-M0 processor?
0
516
views
0
replies
Started
6 months ago
by
Rocker_Hacker
>