Arm Community
Site
Search
User
Site
Search
User
Groups
Arm Research
DesignStart
Education Hub
Graphics and Gaming
High Performance Computing
Innovation
Multimedia
Open Source Software and Platforms
Physical
Processors
Security
System
Software Tools
TrustZone for Armv8-M
中文社区
Blog
Artificial Intelligence
Automotive
Healthcare
HPC
Infrastructure
Innovation
Internet of Things
Machine Learning
Mobile
Smart Homes
Wearables
Forums
All developer forums
IP Product forums
Tool & Software forums
Activity
Support
Open a support case
Documentation
Downloads
Training
Arm Approved program
Arm Design Reviews
More
Cancel
Developer Community
IP Products
Processors
DesignStart
Jump...
Cancel
DesignStart
Blog
Forum
Videos & Files
Jump...
Cancel
New
DesignStart requires membership for participation - click to join
More developer forums
Android forum
Arm Compilers forum
Arm Development Platforms forum
Arm Development Studio forum
Classic processors forum
Cortex-A / A-Profile forum
Cortex-M / M-Profile forum
Cortex-R / R-Profile forum
Embedded forum
GNU Toolchain forum
Graphics and Gaming forum
HPC forum
Keil forum
Machine Learning forum
SoC Design forum
Related tags
ACE
AXI
CHI
Cortex-M
Cortex-M Prototyping System (V2M-MPS2)
Cortex-M0
Cortex-M1
Cortex-M3
Custom SoC
DesignStart
FPGA
Keil
MPI
Simulation
Verilog
Forums
DesignStart forum
Discussion about custom SoC design with Arm IP through the easy-access DesignStart program.
135
questions
RE: Issue with synthesizing Cortex-M0 memory Verilog code
10 days ago
All questions in this Community
By title
By date
By reply count
By view count
By most asked
By votes
By quality
Descending
Ascending
All recent questions and discussions
Unread questions and discussions
Questions and discussions you've participated in
Questions and discussions you've started
Unanswered questions and discussions
Answered questions and discussions
Questions with suggested answers
Questions and discussions with no replies
Not Answered
Issue with synthesizing Cortex-M0 memory Verilog code
0
211
views
1
reply
Latest
10 days ago
by
Eric Zhang
Not Answered
Connecting Custom IP with ARM CortexM1 IP from DesignStart
0
74
views
0
replies
Started
25 days ago
by
josina
Not Answered
How to run the system with a slow clock
0
Cortex-M Prototyping System (V2M-MPS2)
178
views
0
replies
Started
1 month ago
by
urian
Answered
Cannot open downloaded Cortex-M3
0
1010
views
7
replies
Latest
1 month ago
by
Eric Zhang
Not Answered
multi core debug interface for ARM CM3
0
320
views
1
reply
Latest
1 month ago
by
Eric Zhang
Answered
What USB Blaster cable?
+1
FPGA
USB
DesignStart
Cortex-M
Cortex-M Prototyping System (V2M-MPS2)
4897
views
7
replies
Latest
1 month ago
by
Javier4
Not Answered
Questions regarding configuration options for Cortex-M3
0
376
views
1
reply
Latest
2 months ago
by
Junhao
Not Answered
MPS2+ ERROR: FPGA did not respond to reset
0
Cortex-M Prototyping System (V2M-MPS2)
588
views
2
replies
Latest
3 months ago
by
Mahesh
Not Answered
Debugging Cortex M3 softcore processor via JTAG - HS3 (Xilinx FPGA and SoC debugger)
0
Cortex-M3
Debugger
658
views
2
replies
Latest
3 months ago
by
Mahesh
Not Answered
How to implement JTAG in Xilinx CM3 Designstart
0
454
views
1
reply
Latest
3 months ago
by
hechtm
Suggested Answer
How to debug cause of Hard Fault on CortexM0?
0
3 (HardFault)
649
views
3
replies
Latest
3 months ago
by
Sean Houlihane
Not Answered
DesignStart Eval on Terasic MAX10-Standard Board
0
675
views
1
reply
Latest
3 months ago
by
Junhao
Answered
Enabling SWO output in Cortex M3 DesignStart FPGA Xilinx edition?
0
977
views
3
replies
Latest
3 months ago
by
jpthibault
Not Answered
m3 for xilinx,I want to change the ip named aix_quad_spi_0 into the standard spi for a spi tft display,what should I change the io timing part in the xdc file?
0
314
views
0
replies
Started
5 months ago
by
liheyi
Not Answered
when I include xpseudo_asm_rvct.h in keil ，the keil remind me that "error in include chain (xpseudo_asm_rvct.h): expected '(' after 'asm' ". I have not made any changes to the file.
0
493
views
1
reply
Latest
5 months ago
by
Maos1314
>