This white paper is an introduction to porting existing code to the A64 instruction set supported by Armv8-A processors like the Cortex-A53 and Cortex-A57 from Arm. It will also be useful for those writing new code for these platforms.
It seems that is a question with many answers! For some, it will be the need to address more than 4GB of memory, for others the need for wider registers and greater accuracy of 64-bit data processing, for still others the attraction of a larger register set.
Whatever your reason for looking to move to 64-bit, it is likely that you will have a body of legacy software which will need porting as well as new code which needs writing. This paper is designed to help with both processes.
We’ll start with a quick look at the evolution of the Arm architecture which has brought 64-bit to reality.
Thank you for pointing this out. I will work on a minor update and post it shortly.
I have doubt on page 10, In the table that shows alternate instruction for PUSH and POP, In A64, to push and pop x0 and x1 we require 16 byte location in stack. But in the example it shows 8. Could you please comment on this? Thanks!
Thank you for your comment on the document.
C1x and C++11 are shorthand names for the latest ISO/IEC standards for C (C11, ISO/IEC 9899:2011) and C++ (ISO/IEC 14882:2011). Among other things, these standards introduce standard capabilities for multi-threaded programming. This includes the requirement for standard implementations of mutexes and other forms of "uninterruptible object access". The Load-Acquire and Store-Release instructions introduced in A64 are intended to comply with this.
I hope this helps.
As you and others have kindly pointed out, there is a minor error here. The structure will also have 4 bytes of padding added at the end to ensure that it aligns properly when declared as an array.
I will upload a minor update to the document shortly.
Many thanks for pointing this out. I trust that you found the rest of the document useful.
Could someone give me a introduction about "C1x/C++11" in the figure of page 2nd ?