We all know that to get anywhere in life you need to have connections. A good connection will open the right doors for you and ensure that you reach your potential with the minimum of wasted energy. The same is true in the microworld of an SoC! Massive growth in system integration places on-chip communication and interconnect at the centre of system performance. System interconnect fabric is the infrastructure that provides cache coherency, system optimization and power savings. Traffic interactions have become complex and, if left unchecked can cause poor, unpredictable system performance. These days we are seeing ARM technology appear in a wide variety of end applications, from enterprise servers to tiny IoT or wearable devices. In every case, the interconnect fabric is central to ensuring the power and performance requirements for each chip are met. ARM has a range of interconnect solutions that are designed for different purposes across the SoC. The CoreLink interconnect family is the lowest risk solution for on-chip communication. Designed and tested with ARM Cortex® and Mali processors, CoreLink interconnect from ARM provides balanced service for both low latency and high bandwidth data streams. The CoreLink Interconnect family is made up of three product families:
ARM CoreLink Interconnect provide the components and the methodology for designers to build SoCs based on the AMBA specs, maximising the efficiency of data movement and storage, delivering the performance needed at the lowest power and cost. I’ll take you through the options and highlight the use case that each interconnect family is best suited for.
There is a recurring theme at the moment; there is a need for more efficient, optimized solutions from edge to core. ARM Cortex A-Series Processors with CoreLink interconnect IP provide a common architecture across the spectrum, scaling from cost efficient home gateways to high performance core networking and server applications. As networking applications continue to evolve in both throughput and services, we can see their workloads are very different from compute-based ones. That requires a different approach to SoC interconnect, for example in the need for scalability and end to end Quality of Service. The Cache Coherent Network family offers maximum performance with integrated snoop filters and AMBA 5 CHI.
Some of the use cases the CCN family are designed for
On the high end of the performance spectrum, macro base station and cloud applications require dense, efficient compute platforms with the right-sized cores to match the appropriate workload. High performance cores are required for server compute and control plane processing, efficient small cores are required to maximize packet throughput and customized accelerators are needed for Layer-1, security and content delivery processing. Ranging from the largest CCN-512, which supports macro base station and cloud applications, to the smallest CCN-502, which supports small cell base stations and WiFi access points, the CCN family is optimised for all infrastructure applications. In fact, it is estimated that about 80% of network energy consumption is attributed base stations so there is a real need for the hardware to be as efficient as possible. Every cloud has a silver lining - with the massive growth in global data it has forced people to reassess the infrastructure that manages this. CCN is part of a dedicated enterprise server solution that ARM is providing, offering a scalable solution that delivers optimal performance depending on the system PPA requirements.
The Cache Coherent Interconnect offers the smallest and lowest power multi-cluster, perfectly suited for mobile SoCs where PPA restrictions are greater. It represents a step down from the CCN in terms of the size of end-use applications, moving from networking to mobile-based SoCs. Mobile systems designers need to support high resolution screens, complex applications and console quality graphics. The Cache Coherent Interconnect is a critical part of the mobile SoC, it provides full cache coherency between big.LITTLE processor clusters and provides IO coherency for other agents such as Mali GPU, network interfaces or accelerators. The CoreLink CCI-500 was released at the beginning of February and offers a scalable and configurable interconnect which enables SoC designers to meet their performance goals with the smallest possible area and power. CoreLink CCI-500 builds on the market-leading success of the previous generation interconnect in three key areas; reduced system power by integrating a snoop filter, increased CPU memory performance and a massive uplift in system bandwidth. The increase in peak system bandwidth, supporting speeds of up to 34GB/s, paves the way for console-quality gaming and seamless 4K content in next-generation mobile devices. It is optimized for mobile but its configurability means it is also suitable for set top boxes, small enterprise and automotive applications.
Example premium mobile system containing CoreLink CCI-500
Finally, the Network Interconnect provides a fully configurable, hierarchical, low latency, low power connectivity for AMBA. The NIC-400 works with the other CCN and CCI products, making a lot of the microconnections to extend I/O coherency to larger numbers of masters. Additionally, it is used in a number of embedded applications and wearable devices where low power and cost are issues to be considered. It is a simple crossbar switch that can be configured from 32 to 256 bits wide, a must for small geometries and increasing numbers of IP cores. The real beauty of the NIC-400 is its configurability; it can be optimised to suit the requirements of a complex SoC using the AMBA protocols. Interconnect performance in terms of raw clock speed depends on many factors including the configuration, size and the system components it is connected to, and of course the silicon technology it is implemented with. An important feature of the NIC is the ability to configure and enable pipeline register stages at various points in the design. This allows a fine grain control in the trade-off between clock speed, and latency.
CoreLink NIC-400 extends I/O coherency to large numbers of masters
As the IP components in a chip become more specialized one of the jobs of the interconnect fabric will be to suit system design requirements and enable rapid on-chip communication between processors, memory and I/O agents. When developing a modern SoC it is so important to choose IP that is fit for requirements. Whether you are looking to build a large server chip, small WiFi access point, premium mobile system or even extend the I/O coherency across the chip, ARM’s CoreLink interconnect portfolio has something tailored to that purpose.