Recently I presented “Coherent Interconnect Technology Supports Exponential Data Flow Growth” at the Linley Processor conference in Santa Clara, CA where I announced a new ARM coherent interconnect product for enterprise applications, the CoreLink CCN508.
Beyond the introduction of CoreLink CCN-508 my paper described consumers driving data growth creating new challenges for Operators with data traffic expected to grow some 18 times on mobile networks from 2011 to 2016. It is estimated that about 80% of network energy consumption is attributed to base stations. I also discussed networking evolution trends where rapid deployment of new services is key within an open software platform for scaling across HetNet solutions. The industry continues to look for density, power, and cost over raw performance with one size CPU no longer fitting all infrastructure applications. I detailed why ARM is uniquely positioned to address all of these trends, enabling our rapid growth in enterprise/infrastructure using the proven pedigree of CCN (Cache Coherent Network) family of solutions.
If you missed this presentation I will be presenting similar material at ARM TechCon 2013, Session code ATC-222 on Wednesday at 2:30pm. Direct Link:
Part of the ARM building blocks for Enterprise is the CCN (Cache Coherent Network) family of solutions and the new CoreLink CCN-508 is the latest follow-on to the CoreLink CCN-504. CoreLink CCN-508 is the latest highly-scalable solution to come out ARM's enterprise and networking design group.
Figure 1. ARM Enterprise building blocks
In future blogs I will provide additional information how to build different enterprise solutions using ARM CPU and system IP solutions.
The new CoreLink CCN-508 is the latest in the family of ARM interconnects and follows on from its little brother the CoreLink CCN-504 which was successfully introduced and deployed to SiP vendors and OEM partners. Public licensees include LSI and Calxeda and a slew of partners not yet public. Some of the comments we received are below:
“Calxeda and ARM have been working closely to meet the demands of the datacenter since ARM's initial investment in our company in 2008, and we are beginning to see the fruits that relationship,” said Barry Evans, co-founder and CEO, Calxeda. “We are already building our next generation datacenter-class solutions using this new ARM CoreLink technology, and think we will once again send shockwaves across the industry when they are announced.”
“To meet the demands of rapidly growing mobile network traffic, LSI and ARM have worked closely to drive a feature-rich on-chip interconnect that can serve as the backbone for industry-leading many-core system-on-chip devices,” said Gene Scuteri, vice president of engineering, LSI. “ARM expertise in processor and interconnect technology, guided by LSI's deep understanding of networking and compute workloads, has delivered a robust, carrier-grade interconnect that will deliver scalable, deterministic performance and quality of service for today’s most advanced networks.”
The CCN family is not a demo, or concept. It has already been deployed in fully functional silicon running at 1.5+GHz in 28HPM process technology. It has gone through extensive verification with trillions of cycles in simulation and emulation, and more formal techniques and is built to the proven non-blocking AMBA 5 CHI (Coherent Hub interface) and the interconnect micro-architecture. We have used RTL and a very detailed highly accurate performance model to provide performance tuning using internal and external SiP and OEM workloads.
Solutions based around CCN-family products are extremely attractive in the mobile base station market. Jim Anderson, senior vice president and general manager for LSI’s Networking Solutions Group opined on the extent in his recent quote “The delivery of Axxia 5500 means that our customers are now building Axxia processor performance and efficiency into systems that will represent over half of the mobile base station market”
If you want to be able to replace two-socket boards with a more elegant solution, look for products that are based on the CoreLink CCN-508 Cache Coherent Network. CoreLink CCN-508 is a cache coherent network providing support for up to 32 fully coherent cores. Supported cores include Cortex-A57 and Cortex-A53.
We designed CCN-508 to provide support for large core counts while maintaining the power efficiency ARM is famous for. It has integrated snoop filter to minimize snoop bandwidth and a configurable integrated L3 cache scalable from 1MB to 32MB. To maintain the lowest-possible power profile while delivering the performance required to support 32 cores, we included the following low power features:
All of that processing power might be wasted if we did not include extensive support for accelerators and other heterogeneous processing enablers:
o Any ARM-compatible GPU
o ARM-compatible hardware accelerators
o ARM-compatible high speed I/O
To ensure that enough data flows into and out of this SoC, CCN-508 also supports up to four x72 channels of ECC-enabled DDR with direct connection to the CoreLink DMC-520 Dynamic Memory Controller using an AMBA 5 CHI interface.
Figure 2. System diagram of CoreLink CCN-508 based SOC
The CoreLink CCN-504 is the first cache coherent network that ARM launched in 2012. It provides support for up to 16 fully coherent cores. Supported cores include Cortex-A15, Cortex-A57 and Cortex-A53. Like its big brother, it has an integrated snoop filter to minimize snoop bandwidth and a configurable integrated L3 cache scalable from 1MB to 16MB. Low power support includes extensive clock gating, leakage mitigation hooks, granular DVFS and CPU shutdown support, and partial or full level-3 cache shutdown and retention modes. Up to 18 ports of AMBA 4 AXI4/ACE-Lite interfaces are supported for Heterogeneous processing; DSP, GPU, hardware acceleration and high speed I/O. Up to two x72 channels of DDR memory are supported with direct connection to the CoreLink DMC-520 using AMBA 5 CHI interface.
Figure 3. System diagram of CoreLink CCN-504 based SOC
The CoreLink DMC-520 is the 5th Generation ARM dynamic memory controller with support for x72 DRAM DDR3, DDR3L and DDR4 up to DDR4-2667. It supports both registered and unregistered memory for compatibility and system expansion. It supports a direct, low latency AMBA 5 CHI connection to CoreLink CCN-508 and industry standard DFI-3.0 to connect to PHYs. It provides ECC and RAS features and has performance profiling capability and system wide QoS (Quality of Service). It was designed and verified with ARM Cortex CPUs and CoreLink CCN interconnect, and ARM is partnering with a number of 3rd party PHY vendors to offer the complete solution to the pins.
No matter what application focus you have - bursty data path traffic with multiple interfaces; compute intensive control path with low latency requirements; or latency sensitive air interfaces with predictable latency requirements the CoreLink end to end QoS provides solutions for all. There is a control field for every transaction which can be fixed, programmable or regulated. The programmable mechanisms include regulation of traffic on ingress with bandwidth and latency management. Additionally, there is re-ordering and arbitration in the interconnect, integrated L3 and the dynamic memory controller.
Every cloud has a silver lining - There is massive growth in data driving infrastructure change and consequential challenges in managing this change. ARM scalable SoC solutions are the best way to solve these incorporating world class efficient cores, interconnect and memory controllers with a proven pedigree and family history.
It is no wonder that ARM silicon partners use CoreLink CCN family interconnect products to lead in the core count expansion in enterprise applications – the CCN products allow the silicon vendors to focus their design efforts on other key system components, while using optimized power efficient interconnect products from ARM that are designed in tandem with Cortex-A CPUs – truly a winning combination.