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SoC Design forum
The SoC Design community is the place to be when planning, designing, or researching your SoC. Here, we discuss design and implementation, Artisan or other physical IP, manufacturing processes and technology challenges.
358
questions
APB - Purpose of PADDR?
1 day ago
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0
ARM Community
2865
views
0
replies
Started
1 month ago
by
Annie Cracknell
Not Answered
APB - Purpose of PADDR?
0
APB
APB Peripherals
AMBA 3 APB Interface
AMBA 2 APB Interface
45
views
0
replies
Started
1 day ago
by
Kyle Kochan
Not Answered
Does it use a Slow Clock to turn off Main Clock?
0
91
views
0
replies
Started
9 days ago
by
Ridge Mao
Answered
Can re-order depth affect functionality of write transaction?
0
688
views
5
replies
Latest
10 days ago
by
Colin Campbell
Not Answered
Alignment Address Calculation in AHB
+1
AMBA
AHB
Interface
11352
views
5
replies
Latest
12 days ago
by
Colin Campbell
Not Answered
HTRANS when HREADY is low on the 2nd HCLK after starting the transfer
0
AMBA 3 AHB Interface
AHB
356
views
1
reply
Latest
12 days ago
by
Colin Campbell
Answered
AMBA TLM 2.0 Library & AMBA-PV Extensions to TLM
+1
1208
views
3
replies
Latest
28 days ago
by
Toshihisa Oishi
Not Answered
Does CoreSight support ThunderX2 server?
0
CoreSight
800
views
0
replies
Started
1 month ago
by
hi-watanabe
Not Answered
How to calculate AXI interleave depth and reorder depth.
0
AXI4
1898
views
0
replies
Started
1 month ago
by
hungtaowu
Not Answered
AHB two-cycle Response
+1
2231
views
1
reply
Latest
1 month ago
by
Colin Campbell
Not Answered
Looking for manufacturer to produce our motherboard design
0
11122
views
1
reply
Latest
1 month ago
by
Ibrahim112
Not Answered
In APB, for data bus width, can I increase from 32 bits(default) to 64 bits(as per my project requirements)?
0
APB
AMBA 2 APB Interface
3827
views
1
reply
Latest
1 month ago
by
Colin Campbell
Not Answered
what is "transfer" signal mentioned in the APB state diagram? Can I use "PSELx" signal to determine transfer is going to happen?
0
APB
AMBA 2 APB Interface
3671
views
1
reply
Latest
1 month ago
by
Colin Campbell
Not Answered
Can secure states know that they are in secure state?
0
3882
views
0
replies
Started
2 months ago
by
chenyinhua
Not Answered
L4 cache in N1 SDP SoC
0
4233
views
2
replies
Latest
2 months ago
by
Oliver Beirne
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