Hello,For my bachelor thesis I have to implement the RTL-Code of the Cortex-M3 in the DE-10 Standard Board.The FPGA on the Terasic DE-10 Standard is the Cyclone V 5CSXFC6D6F31C6.If I try to compile the ".sof" file of the Eval package in Quartus Prime file, I get the error that there are not enough i/os (430 required, 288 available).If I try it on the Terasic DE2-115 with the Cyclone IV EP4CE115F29C7N I get the error "can't place all RAM cells in design".My questions:Is it possible to adapt the design to the I/O and/or the RAM-structure?Do I have to do that manually in Quartus Prime?
I don't want to create an ASIC chip. I just want to implement the the IP on the FPGA with Quartus Prime on Windows and eventually extend the code with custom IP. The 2 IPs are connected with AMBA. After that I want to create a test program for the Cortex-M3 IP via Keil on Windows.
Is this possible?
I don't really have the time to set up and learn Linux RedHat.
Yes, it is all possible. The IP is in verilog, and you can use the Windows tools that you're familiar with. We do provide Keil project files for our example test programs which work in Windows. What we don't provide is a simulation environment in Windows - but that can be based on the tools you're familiar with and each user will obviously have their own preferences here.
One more question. If I want to implement the RTL Code in Quartus Prime, do I have to take the logic files from the Cortex-M3 Global Bundle or the CoreLink SSE-050 Subsystem Global Bundle first?
I think if there are similar files in both deliverables, then the SSE-050 ones will be the ones you need.
I thought that the subsystem is just around the processor to edit and extend the design? Or how can I understand it?