Hello,For my bachelor thesis I have to implement the RTL-Code of the Cortex-M3 in the DE-10 Standard Board.The FPGA on the Terasic DE-10 Standard is the Cyclone V 5CSXFC6D6F31C6.If I try to compile the ".sof" file of the Eval package in Quartus Prime file, I get the error that there are not enough i/os (430 required, 288 available).If I try it on the Terasic DE2-115 with the Cyclone IV EP4CE115F29C7N I get the error "can't place all RAM cells in design".My questions:Is it possible to adapt the design to the I/O and/or the RAM-structure?Do I have to do that manually in Quartus Prime?
This is expected that a design for one FPGA won't 'just work' if you change the device. There is nothing that fundamentally stops you doing this, but there are several things to be aware of. It is not a process which we support, but I'd encourage you to share your top level files, scripts and results if you can. Note that only a limited set of files are OK to redistribute though.
The Cortex-M3 DesignStart Eval RTL Customization Guide has a few pointers, but here are a few thoughts that your question touches:
I hope this gives you some useful ideas.
Thanks for the huge amount of information. I think I will try to modify the Eval-RTL code first, to get an overview of the whole system. Is it possible to just set the unused pins to zero? Otherwise I would try to make a top_top level file over my top_level, to set the pins manually.
Just trim the signal list, and remove the constraints for the signals you remove.
I trimmed unused signals, that my design would compile eventually. I also had to trim one 32-bit RAM block to be under 288 pins to compile. Unfortunately the design uses 32-bit and 64-bit SSRAM, while my board uses 16-bit SDRAM.
So I have to match the different RAMs? Is that even possible?
I assume with the Pro version I can adjust my design more to my hardware? So maybe I'll study the Pro documentation and try to build my customized design?
You can decide if you need to implement access to the external in-board RAMs. The design should function without these.
If you want to use your 16 bit RAM, you will need an AHB-to-RAM interface which handles 32 bit read/write accesses, performing 2 external accesses - it's certainly easy to do (if not entirely trivial).
I tried to figure out the Pro version, but there is no hint for setting up the design in Windows, only in Linux. Is there a way to set it up in Windows?
We don't support Windows for pro, as we are expecting that the majority of Pro users will be using ASIC tools, and will have a Linux environment for this. Automation is also easier in Linux. Pro only provides a simulation flow, or support for a 3rd party implementation flow. You can compile the Pro software examples in Keil under windows, but that is the extent of what we currently provide.
I don't want to create an ASIC chip. I just want to implement the the IP on the FPGA with Quartus Prime on Windows and eventually extend the code with custom IP. The 2 IPs are connected with AMBA. After that I want to create a test program for the Cortex-M3 IP via Keil on Windows.
Is this possible?
I don't really have the time to set up and learn Linux RedHat.
Yes, it is all possible. The IP is in verilog, and you can use the Windows tools that you're familiar with. We do provide Keil project files for our example test programs which work in Windows. What we don't provide is a simulation environment in Windows - but that can be based on the tools you're familiar with and each user will obviously have their own preferences here.
One more question. If I want to implement the RTL Code in Quartus Prime, do I have to take the logic files from the Cortex-M3 Global Bundle or the CoreLink SSE-050 Subsystem Global Bundle first?
I think if there are similar files in both deliverables, then the SSE-050 ones will be the ones you need.
I thought that the subsystem is just around the processor to edit and extend the design? Or how can I understand it?