DesignStart Eval on Terasic DE10-Standard Board

Hello,

For my bachelor thesis I have to implement the RTL-Code of the Cortex-M3 in the DE-10 Standard Board.
The FPGA on the Terasic DE-10 Standard is the Cyclone V  5CSXFC6D6F31C6.

If I try to compile the ".sof" file of the Eval package in Quartus Prime file, I get the error that there are not enough i/os (430 required, 288 available).

If I try it on the  Terasic DE2-115 with the Cyclone IV EP4CE115F29C7N I get the error "can't place all RAM cells in design".

My questions:
Is it possible to adapt the design to the I/O and/or the RAM-structure?
Do I have to do that manually in Quartus Prime?

Is there another way to compile the RTL-Code on the board than in Quartus Prime?
I read the documentation of the DesignStart Eval, but couldn't find something about this subject.

Thank you in advance.
Parents
  • try to compile the Cortex-M design start at the SYSTEM level (the top module name should be cmsdk_mcu.v), not PROCESSOR level.

    The port list of SYSTEM level for the kit should be CLK, RESET, SWI, SWCLK, P0 (16-bit), P1(16-bit)... totally less than 50 I/O pins, I think.

Reply
  • try to compile the Cortex-M design start at the SYSTEM level (the top module name should be cmsdk_mcu.v), not PROCESSOR level.

    The port list of SYSTEM level for the kit should be CLK, RESET, SWI, SWCLK, P0 (16-bit), P1(16-bit)... totally less than 50 I/O pins, I think.

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