Hello,For my bachelor thesis I have to implement the RTL-Code of the Cortex-M3 in the DE-10 Standard Board.The FPGA on the Terasic DE-10 Standard is the Cyclone V 5CSXFC6D6F31C6.If I try to compile the ".sof" file of the Eval package in Quartus Prime file, I get the error that there are not enough i/os (430 required, 288 available).If I try it on the Terasic DE2-115 with the Cyclone IV EP4CE115F29C7N I get the error "can't place all RAM cells in design".My questions:Is it possible to adapt the design to the I/O and/or the RAM-structure?Do I have to do that manually in Quartus Prime?
try to compile the Cortex-M design start at the SYSTEM level (the top module name should be cmsdk_mcu.v), not PROCESSOR level.
The port list of SYSTEM level for the kit should be CLK, RESET, SWI, SWCLK, P0 (16-bit), P1(16-bit)... totally less than 50 I/O pins, I think.
I only got the following files in the hierarchy.
I tried to set the "fpga_system" as top module, but there is still the same error. Am I missing some files in this project?
Can you clarify what changes you have made to target your specific device, and how you trimmed the design to result in the file list above?
In the standard design, you can see the directories which are used:
grep SEARCH_PATH AN511_SMM_CM3DS.qsf
You can also see the I/O pin assignment specification like this:
grep set_location_assignment AN511_SMM_CM3DS.qsf
I recently got the DesignStart Pro packange from my professor to set up my design on the board. I just have to figure out how it works before I can start. But I will reply you if I make progress.
At least for your initial investigations, DesignStart Eval might be easier to work with. The packaging is a little more targeted at a specific design. If you start from pro, you need to build more of the system yourself. (You'll still need to modify the upper levels of the design though).
Okay you recommend setting up the Eval version first, before I begin with the Pro, although I have to use the Pro version for my thesis?
Depends on the constraints... Eval is a finished FPGA port of the design, Pro is the core subsystem which eval is built around. The core from Pro will precisely drop in to the eval design for example.
Another way to look at it, Pro assumes you're manufacturing an SoC, so will be adding your own IP, and also adding all the infrastructure such as clock/reset, regulators, pad-ring, etc. For this reason, the integration in Pro stops at a lower level. There might not be much difference, but this is where I'd start for another port...