Cortex-M0 DesignStart R2

That is a bit misleading, but I don't believe it's the problem, since the version we've been testing in FPGA is the same. With M0, there are no other CoreSight components which would need to be enumerated in the ROM table, and I believe that tools ought to discover the CPU regardless in this scenario.

We've only tested debug using the Arm toolchains - and there you can see both the probe and the SW-DP identified. The important part to confirm that the FPGA is correct would be the box at the top right here.

That is a bit misleading, but I don't believe it's the problem, since the version we've been testing in FPGA is the same. With M0, there are no other CoreSight components which would need to be enumerated in the ROM table, and I believe that tools ought to discover the CPU regardless in this scenario.

We've only tested debug using the Arm toolchains - and there you can see both the probe and the SW-DP identified. The important part to confirm that the FPGA is correct would be the box at the top right here.

Trying to connect, I get

SEGGER J-Link Commander V6.00d (Compiled Jul 29 2016 19:08:27)
DLL version V6.20b, compiled Sep 22 2017 17:57:26

Connecting to J-Link via USB...O.K.
Firmware: J-Link V9 compiled Sep 22 2017 17:42:08
Hardware version: V9.30
S/N: 269300240
License(s): FlashBP, GDB
OEM: SEGGER-EDU
VTref = 0.000V


Type "connect" to establish a target connection, '?' for help
J-Link>connect
Please specify device / core. <Default>: CORTEX-M0
Type '?' for selection dialog
Device>?
Please specify target interface:
  J) JTAG (Default)
  S) SWD
TIF>s
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>5
Device "CORTEX-M0" selected.


Cannot connect to target.
J-Link>connect
Device "CORTEX-M0" selected.

I changed from J-Link to ULINK pro:

Looks much better, however:

.

I'm not sure what is going on with J-link there - maybe it does the power-up implicitly (and fails).

Not powering up would suggest to me that the CDBGPWRUPREQ to CDBGPWRUPACK loopback (L595 in user_partition under RevC) is missing. This is a CoreSight requirement, even if there is no power control implemented, you need to provide the illusion to the tools that they can both enable and disable debug power.

Sean

Ok, I put the code from user_partition into my design and added the necessary connections. Unfortunately, the result remains the same.

A few things to check:

1) Check reset type to System Reset Request to see if it helps

2) I think the SWJ option can be uncheck as the Cortex-M0 DAP don't have protocol switching

3) Connection of SYSRESETREQ (System Reset Request) - can it generate a system reset?

4) JTAG/SWD clock constraints in synthesis, is it missing?

Hope it helps.

regards,

Joseph

Another suggestion I've had is that maybe there is a clocking or reset with the core domain (since the DAP ID registers are in the SWCLK domain), affecting wither the core or the CDBGPWRUPREQ/CSYSPWRUPREQ and the corresponding acknowledge signals.

If you carry on with ULINKPro for now (we should follow the JLINK problem later), it will be useful to enable the logging:

Dear Sean, dear Joseph,

I solved parts of the problem on Saturday:

your suggestion with the CDBGPWRUPREQ to CDBGPWRUPACK loopback was right.

I copied the code, but forgot the CDBGPWRUPREQ   connection.

So I had

   .CDBGPWRUPREQ    (),
   .CDBGPWRUPACK     (CDBGPWRUPACK),

instead of

   .CDBGPWRUPREQ    (CDBGPWRUPREQ),
   .CDBGPWRUPACK     (CDBGPWRUPACK),

I am now able to download and debug.

I will now try with J-Link and then do the next steps.

I am very grateful for you help and support.

Regards,

Eberhard