Wenkwei asked: "with the M3 designstart CMSDK, is it possible to design multi-master bus? In the IoT Cortex-M TRM, only an ahb-lite structure is illustrated. That document does mention AHB and APB expansion through INTEXP[1:0] but what if there are more than two masters I need to support?"
Yes, full AHB can be connected to Lite with a simple wrapper. Generally I don't think it makes sense to build a full AHB matrix since this ends up with lower bandwidth and worse latency, but it depends on your system constraints. Multi layer is an alternative to the full AHB arbitration, and it adds additional data paths so it is probably the best general solution.