Wenkwei asked: "with the M3 designstart CMSDK, is it possible to design multi-master bus? In the IoT Cortex-M TRM, only an ahb-lite structure is illustrated. That document does mention AHB and APB expansion through INTEXP[1:0] but what if there are more than two masters I need to support?"
The SSE-050 subsystem in the Cortex-M3 DesignStart example uses a multi-layer AHB-Lite interconnect. As you observe it has 2 expansion ports available (one is needed for the FPGA infrastructure if you need to keep the option of prototyping).
When you need to connect several additional AHB masters to your system, there are two ways you could do this - the best choice depends on how your system needs to perform and the level of activity performed by the masters:
There are other ways that you can enable messages to be passed between different parts of the system, by designing slave components which interface to more than one master - you have a lot of flexibility to optimise your design to the specific solution which you're developing. It's important to check that the latency and throughput of the final choice work in your product and give a good power and area performance at the same time.
With Multi-layer AHB-Lite, Do I need to make AHB-LITE interface masters at all? How about if I have AHB interface masters and slaves and I want to implement them to the Multi-layer AHB-Lite interconnect. Can I just use AHB-full masters and slaves to the AHB-Lite interconnect or do I need to make them to have the AHB-LITE interface?
If you are connecting to a full AHB component to an AHB-Lite port, you will need to tie off some of the signals which relate to granting access to the bus. The significant difference between full and Lite is how the arbitration between different managers is implemented. In multi-layer AHB-lite, this is performed at each subordinate, allowing more than one access to occur at once.
Hi Sean, Thanks you for reply.
You mean that a full AHB component need to make as a AHB-Lite component by tie off some of signals if I want to use it in AHB-Lite port. Thanks.
I have one more doubt that how do I expand a ML full AHB or a full AHB bus from an AHB-Lite environment.
Do I need to make a module which interfaces with both AHB-Lite port and full AHB port?
Yes, full AHB can be connected to Lite with a simple wrapper. Generally I don't think it makes sense to build a full AHB matrix since this ends up with lower bandwidth and worse latency, but it depends on your system constraints. Multi layer is an alternative to the full AHB arbitration, and it adds additional data paths so it is probably the best general solution.