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How do I get the waveform dump file in simulate?

ele

Hi.

I'd like to get the simulation waveform dump file when I do run the simulation of AT421-MN-80001.

there is some options in makefile such as 

# NC verilog option
NCSIM_OPTIONS = -unbuffered -status -LICQUEUE -f ncsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC +TarmacI +TarmacM +TarmacR +TarmacB +TarmacE
NC_VC_OPTIONS = -f $(TBENCH_VC)

after all test passed, I can't find any waveform dump file of nc.

would you please let me how do I get the waveform of the at421 simulation?

and I find someting snap. but I don't know what am I supposed to do with this snap..  

Would yo uplease let me know does anyone know this to use?

Parents
  • +1

    Each supplier of Verilog simulators typically has their own specialised ways of generating optimised trace files, thus a better / tool-specific set of commands can likely be found in your Verilog simulator's documentation, however, the Verilog standard's portable way of generating waveforms is to add something like the following to a module in one of your Verilog files:

    initial
  begin
    $dumpfile("waveforms.vcd");
    $dumpvars(0,top);
  end

    where "top" should be replaced with the name of the top-most module in your design.

    Note that in addition, for NC-Verilog to produce anything other than an empty set of waveforms, you will likely need to ensure that either "-access+r" or "+access+r" are used during compilation.

    Running the simulation will now produce a "waveforms.vcd" file, which, if you're using NC, can likely be viewed via "simvision waveforms.vcd".

    Best regards

    Simon.

Reply
  • +1

    Each supplier of Verilog simulators typically has their own specialised ways of generating optimised trace files, thus a better / tool-specific set of commands can likely be found in your Verilog simulator's documentation, however, the Verilog standard's portable way of generating waveforms is to add something like the following to a module in one of your Verilog files:

    initial
  begin
    $dumpfile("waveforms.vcd");
    $dumpvars(0,top);
  end

    where "top" should be replaced with the name of the top-most module in your design.

    Note that in addition, for NC-Verilog to produce anything other than an empty set of waveforms, you will likely need to ensure that either "-access+r" or "+access+r" are used during compilation.

    Running the simulation will now produce a "waveforms.vcd" file, which, if you're using NC, can likely be viewed via "simvision waveforms.vcd".

    Best regards

    Simon.

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