After compiling the MPS2+ FPGA designstart project (unmodified, as-is out of the box), i'm failing to run it on the FPGA.
While the already downloaded image that arrives on the FPGA runs fine (i run the demo application), the image I compiled fails to run. After the FPGA configuration finishes the LCD remain blank, all the leds are constantly lightened and the LOG.txt (in the root directory of the board) shows the following message: "SMSC9220 initialisation failed."
Also, i see the following messages in Quartus:
I'll appreciate your advice.
Thanks for the quick answer.
We're using Quartus 15.1 and MPS2+ v3.0 (we understood in a previous thread that that's the configuration we need to use).
Hi Eli, I had one of the team look at the log.txt and it looks ok in that the images are loading but stalling probably because the user partition is non functional. Looking at your Quartos screen shot there are lots of clock warnings, have you performed any simulation of your design?
Can I just confirm you are using Quartos Prime (not the free web version) and you have already got the PR licence from ARM?
I see from your log file:
Configuring FPGA from file \MB\HBI0263C\Eli\387st_04.rbeFPGA config: PASSEDPartial reconfiguration of FPGA from file \MB\HBI0263C\Eli\387us_03.rbf
This shows that you are running version 04 of the encrypted image (the rbe file) with version 03 of the partial configuration file (the rbf file).
This will not work.
I am not certain what you mean by "MPS2+ v3.0" and which thread you are referring to, so please excuse me if I'm repeating stuff you already know..
There is a known issue with the MPS2+ deliverables version CMPS3.1 where there is the mismatch between versions of these 2 files. You will need to use version CMPS3.0 available via the Download link at the top right here: https://silver.arm.com/browse/VEM30
You will need to load the recovery image from CMPS3.0 onto your board before following the DesignStart instructions - we recommend you re-format the boards SD card first. See the "System Recovery" image in the CMPS Getting Started Guide.
Hi Eli, another idea we had was we wanted to confirm you have not changed fpga_top.v fpga_system.v, core_partition_shell.v or user_partition.v inputs or output ports. These need to remain the same to that the two partitions connect together correctly.
I haven't changed any file.
I've done the following steps (unchanged Designstart out of the box project):
1. Installed CMPS3.0 on my Windows
2. Copied the CMPS3.0 to my Linux
3. Entered the synthesis directory
4. Launched Quartus (15.1 with PR license), loaded the SMM_M0DS_AN387.qpf project and run compilation
5. Run TCL script
6. Copied RBF to the FPGA
Regarding version 03 vs. 04 - the TCL script produces the file with extension _03. As I understood from the "Cortex-M0 Dwsignstart FPGA prototyping kit" PDF, the extension is just for my tractability of images on the FPGA. Am I wrong? Should I change the version of the encrypted file?
Have you copied the Recovery image from CMPS3.0 onto your board (following the "System Recovery" instructions in the CMPS Getting Started guide).
I downloaded the base image (*.rbe) from CMPS3.0 to the FPGA and it worked.
Indeed the base image that we received with the board is incompatible with CMPS3.0 user partition.
That's good to hear.
Indeed good news, thanks for your support!
Just a followup question:
Are the clock related warnings in my screenshots are expected? Should I ignore them?
The warnings are expected, they're mostly a side effect of the way that clocks are used for the PR flow.
this is what I get using the CMPS_3_1 files: