I have a question about the size of synthesized logic for Cortex-M0 DesignStart processor.
When I use ISE of Xilinx to synthesize Cortex-M0 DesignStart processor (version r1p0-00rel0), I have result as below.
(I configure for using Spartan-3AN, XC3S200AN, Grade = -4 in ISE).
As Xilinx's mention at this link http://www.xilinx.com/publications/archives/xcell/Xcell64.pdf , they used around 3,000 LUT4
for Cortex-M1 (1,900 LUT4 at page 59 + 1,100 LUT4 at page 56 if Cortex-M1 included MMU block).
Have you ever synthesized Cortex-M0 DesignStart processor by ISE of Xilinx? I want to compare my result with yours. Because I need
to map the synthesized gate into Spartan-3AN XC3S200AN, but the overmapped occurred at 4 input LUT4 and Slices as my
If you have any idea for this, please send me in this topic.
PS: I am not know my post is suitable in this area or not. If it is not suitable, you can move it to another one and inform me the new