Cortex-M0 DesignStart processor size (FPGA)?

Dear sirs,

I have a question about the size of synthesized logic for Cortex-M0 DesignStart processor.

When I use ISE of Xilinx to synthesize Cortex-M0 DesignStart processor (version r1p0-00rel0), I have result as below.

(I configure for using Spartan-3AN, XC3S200AN, Grade = -4 in ISE).

Cortex-M0_processor.png

As Xilinx's mention at this link http://www.xilinx.com/publications/archives/xcell/Xcell64.pdf , they used around 3,000 LUT4

for Cortex-M1 (1,900 LUT4 at page 59 + 1,100 LUT4 at page 56 if Cortex-M1 included MMU block).

Have you ever synthesized Cortex-M0 DesignStart processor by ISE of Xilinx? I want to compare my result with yours. Because I need

to map the synthesized gate into Spartan-3AN XC3S200AN, but the overmapped occurred at 4 input LUT4 and Slices as my

attached picture.

If you have any idea for this, please send me in this topic.

PS: I am not know my post is suitable in this area or not. If it is not suitable, you can move it to another one and inform me the new

link.

Thanks.

  • Hello Jack, sorry that no-one got back to you on this question in a timely fashion.

    Yes, the design is too large for that device. You would need to move up to a larger capacity part.

    Using the requested device:

    Design Summary:
    Number of errors: 2
    Number of warnings: 4
    Logic Utilization:
    Number of Slice Flip Flops: 845 out of 3,840 22%
    Number of 4 input LUTs: 4,888 out of 3,840 127% (OVERMAPPED)
    Logic Distribution:
    Number of occupied Slices: 2,495 out of 1,920 129% (OVERMAPPED)
    Number of Slices containing only related logic: 2,495 out of 2,495 100%
    Number of Slices containing unrelated logic: 0 out of 2,495 0%
    *See NOTES below for an explanation of the effects of unrelated logic.
    Total Number of 4 input LUTs: 4,989 out of 3,840 129% (OVERMAPPED)
    Number used as logic: 4,888
    Number used as a route-thru: 101

    The Slice Logic Distribution report is not meaningful if the design is
    over-mapped for a non-slice resource or if Placement fails.

    Number of bonded IOBs: 136 out of 141 96%
    Number of BUFGMUXs: 1 out of 8 12%

    Average Fanout of Non-Clock Nets: 3.77

    Using a larger device:

    Design Information
    ------------------
    Command Line : map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off
    -c 100 -o CORTEXM0DS_WRAPPER_map.ncd CORTEXM0DS_WRAPPER.ngd
    CORTEXM0DS_WRAPPER.pcf
    Target Device : xc3s400
    Target Package : pq208
    Target Speed : -4
    Mapper Version : spartan3 -- $Revision: 1.55 $
    Mapped Date : Wed Mar 15 17:04:42 2017

    Design Summary
    --------------
    Number of errors: 0
    Number of warnings: 5
    Logic Utilization:
    Number of Slice Flip Flops: 841 out of 7,168 11%
    Number of 4 input LUTs: 4,930 out of 7,168 68%
    Logic Distribution:
    Number of occupied Slices: 3,055 out of 3,584 85%
    Number of Slices containing only related logic: 3,055 out of 3,055 100%
    Number of Slices containing unrelated logic: 0 out of 3,055 0%
    *See NOTES below for an explanation of the effects of unrelated logic.
    Total Number of 4 input LUTs: 5,030 out of 7,168 70%
    Number used as logic: 4,930
    Number used as a route-thru: 100

    The Slice Logic Distribution report is not meaningful if the design is
    over-mapped for a non-slice resource or if Placement fails.

    Number of bonded IOBs: 136 out of 141 96%
    Number of BUFGMUXs: 1 out of 8 12%

    Average Fanout of Non-Clock Nets: 3.81

    The slight discrepancies in the numbers are because the second design ran to completion, whereas the first died quite early.