AHB-Lite Back to Back transfer

Dear All,

I'm trying to understand about the back to back concept in AHB(AHB-Lite). Here's I found https://developer.arm.com/documentation/ihi0011/a/AMBA-APB/Interfacing-APB-to-AHB/Back-to-back-transfers article.

As I understand, the AHB "Back-to-Back" means that the ability of the bus to handle multiple transactions in quick succession without any delay or pause. The AHB bus can handle the back-to-back transactions, with no delay or wait between them. 

But I'm confuse that the meaning of back to back transfer. As you can see the image I attached, I think this is not back to back transfer because ADDR3 3 wait states to complete the transaction.

Another example is that the SRAM directly interfacing with AHB-Lite Transfer needs at least 3 cycles , during the processing it must be in a wait state(HREADY Low). So can we say this is also Back-to-Back Transfer?

Could you please clarify what no-delay or wait means in the Back-to-Back Transfer?