AHB-Lite Back to Back transfer

Dear All,

I'm trying to understand about the back to back concept in AHB(AHB-Lite). Here's I found https://developer.arm.com/documentation/ihi0011/a/AMBA-APB/Interfacing-APB-to-AHB/Back-to-back-transfers article.

As I understand, the AHB "Back-to-Back" means that the ability of the bus to handle multiple transactions in quick succession without any delay or pause. The AHB bus can handle the back-to-back transactions, with no delay or wait between them. 

But I'm confuse that the meaning of back to back transfer. As you can see the image I attached, I think this is not back to back transfer because ADDR3 3 wait states to complete the transaction.

Another example is that the SRAM directly interfacing with AHB-Lite Transfer needs at least 3 cycles , during the processing it must be in a wait state(HREADY Low). So can we say this is also Back-to-Back Transfer?

Could you please clarify what no-delay or wait means in the Back-to-Back Transfer?

  • It's hard to tell in their diagram because they do not show HTRANS but it means that HTRANS does not go to an idle state between each transaction. T1, T2, T3 and T7 all start a new transaction. Note that it does not require a dead state between them. The wait states are dictated by HREADY, not by the protocol.