Inconsistency with ATPG model / Verilog-Sim model

Hi All,

I am having trouble with the Tetramax-ATPG simulation.

I am designing a TSMC 40nm SoC and am using the IO library provided by ARM. ATPG and Verilog-Sim models are provided.

I am creating a pattern with Tetramax using an ATPG model.However, the pattern FAIL occurs in the simulation.

The problematic part is the IO cell of bidi port, which is (exp = 0 / got = z).The frequency is FAIL for 1 pattern out of 1000 patterns.

As a test, I do a simulation (NC-Verilog) with an ATPG model without using the Verilog-Sim model, it will pass.

I check the simulation waveform, in Verilog-Model, Z is input from PAD and X is propagated inside.

In the ATPG model, Z is not confirmed at all and is either 0/1.

The port does not have OEN fixed, but it is not SCAN-IN / SCAN-OUT, so it is not fixed.

Verilog-Model was unreadable by Tetramax (Error), so I couldn't use the solution.

I assume that the inconsistency between the Verilog-Model and the ATPG model is the obvious cause, but have you ever experienced such an event?

If you know, please tell me the solution. 

Thank you. Best Regards