I'm trying to load the block diagram for the arty a7 M1 example project. I get this error:
[BD 41-1712] The specified IP 'xilinx.com:ip:axi_bram_ctrl:4.0' does not support the current part 'xc7a35ticsg324-1L'
Any thoughts on how to get past this? Weirdly, the Xilinx docs for that IP seem to support the idea that it's not supported on the xc7a35 part.
Thanks Matthias! That worked for me, and I'm running Vivado 2018.3 on Windows 10.
Thanks Mathias! This seems to work for me, too, and I'm running Vivado 2019.1 on Windows 10. I was able to Validate in the block diagram view