FPGA Prototyping walkthrough using Arm Cortex-M0 DesignStart and MPS2

This article relates to AN387 Cortex-M0 DesignStart delivered with the MPS2 board.

For Cortex-M0 DesignStart Eval (AT510) r2p0-00rel0, see the ”Arm Cortex-M0 DesignStart Eval FPGA Revision: r2p0 User Guide” document that is delivered as part of the AT510-MN-80001-r2p0-00rel0 bundle.

Introduction

DesignStart components

The Cortex-M0 DesignStart program consists of a number of components. These include:

• The Cortex-M0 DesignStart Design Kit facilitates Verilog design and simulation of a prototype SoC based on the Cortex-M0 DesignStart processor. The Cortex-M0 DesignStart processor is delivered as a preconfigured and obfuscated, but synthesizable, Verilog version of the Cortex-M0 processor which allows for Verilog HDL design and simulation of a prototype SoC-based on the Cortex-M0 DesignStart processor.
• The Cortex-M0 DesignStart FPGA Prototyping Kit provides an encrypted FPGA image of the Cortex-M0 DesignStart processor together with a customizable example subsystem including AHB and APB components. The example subsystem delivered with the FPGA prototyping kit is modifiable, allowing the user to customize logic surrounding the DesignStart processor. 
• The Arm Cortex-M System Design Kit (CMSDK) provides example AMBA systems offering a library of fundamental peripherals and interconnect along with software drivers and examples.
  The example subsystem provided with DesignStart is a subset of CMSDK.

For more information about these components and how a developer can use them, see the White Paper which also give further detail on using the Cortex-M0 DesignStart Design Kit.

Arm MPS2 board and FPGA prototyping system

The Cortex-M0 FPGA Prototyping Kit can only be used with the Arm MPS2 and MPS2+ boards, because the encrypted FPGA core image can only be decrypted by a key pre-installed on these boards. The older MPS2 board is no longer available for purchase. MPS2+ has twice the FPGA area to the MPS2 board.

The Arm MPS2(+) board implements a Cyclone V FPGA to provide a development environment for demonstration and software validation using Fixed FPGA implementations of the Cortex-M class family of processors, as well as FPGA prototyping. See Arm Developer for further details.

Building and running the DesignStart FPGA bitfile

This section is intended to give a step by step guide to installing the various software required to build the DesignStart FPGA bit file, then download and run it on the MPS2(+) board.

1. Accessing the MPS2 deliverables

The set of software deliverables that come with the MPS2(+) boards is known as the Cortex-M Prototyping System (CMPS). The deliverables can also be accessed from Arm Silver Downloads under Development Tools | Versatile Family | Versatile: Board Support Files | Cortex-M Prototyping System version x.y (where x.y is the version number). Please note that instructions in this document are only relevant to CMPS version 3.0 and later:

Figure 1: Select the required CMPS Download

Downloading the deliverables requires acceptance of an End User Licensing Agreement.

NOTE: There is a known issue with the DesignStart project in CMPS version 3.1 which is the version delivered with the MPS2+ board. There is a mismatch between the board files and the source files within the project. Although the source files synthesize correctly, the resulting bit file will not run with the board files in the project. Currently the only way to get around this for customers wanting to work with DesignStart project on MPS2(+) is to use CMPS version 3.0.

2. Install CMPS

The CMPS Deliverables contain a Windows installer. When run this will install the deliverables, by default, in the C:\Program Files (x86)\CMPS_x_y folder (x and y being the version number as discussed above). See the CMPS Getting Started Guide that comes in the deliverables for more introductory information about the board and using the deliverables.

3. Access the DesignStart FPGA prototyping project AN387

The Cortex-M0 DesignStart FPGA Prototyping Kit is provided within the CMPS in the form of Application Note 387, alongside the App Notes which contain the fixed FPGA image deliverables for each of the Cortex-M cores.

The C:\Program Files (x86)\CMPS_x_y\ app_notes\AN387 folder contains the Cortex-M0 FPGA DesignStart project, including source files, and the encrypted DesignStart Cortex-M0 core FPGA image.  There is also a docs folder containing the documents referenced below.

Figure 2: Locate the App Note AN387 folder

4. Access/install Quartus Prime

In CMPS v3.0 and later, the customization process within the Cortex-M0 FPGA Prototyping Kit relies on technology supplied by Altera’s Quartus FPGA design tool called partial reconfiguration. (CMPS versions prior to v3.0 required access to separate licensed core IP).

To build the FPGA files, Altera Quartus Prime Standard Edition is required (not Quartus Prime Lite). In order to enable the partial reconfiguration feature, an additional (free of charge) license is required to the basic Quartus Prime subscription edition license. Please refer to this FAQ for more information on this.

Quartus Prime installers can be downloaded from here. To build AN387 you only require the Cyclone V device file and Quartus Prime components. The FPGA project provided has been tested successfully with Quartus Prime version 15.1. At time of writing there is a known problem with DesignStart not working in Quartus Prime versions 16.0 and later, so we recommend working with version 15.1.

Figure 3: Select the required Quartus components for Download

5. Build and load the FPGA bitfile

The document DAI0387z_cortex_m0_design_start_fpga_prototyping_kit.pdf, (where z is the latest document version) can be found in the ….\AN387\docs folder. This document provides further information about the components of DesignStart that were briefly outlined above, along with instructions on how to build the FPGA bit file from the provided source code.

Section 7 “FPGA Build Guide” gives further information about the build requirements. It describes the layout of the FPGA project. In particular, the way the system is partitioned, along with code layout and restrictions.

Section 7.4 gives step by step instructions for building and loading the FPGA image. Following these instructions will help you open the synthesis project, compile the design and build the bitfile using Quartus Prime.

Finally, the instructions explain how to download the resultant bitfile onto the SD card of the MPS2 board, and how to edit the configuration files in order to load the bitfile into the FPGA and run the DesignStart system on the board.

When the MPS2(+) board powers up and runs, a LOG.txt file is created in the base folder on SD card. This file can give useful information for debugging if the board fails to run as expected.

Further development and prototyping

As mentioned earlier The Cortex-M0 DesignStart Design Kit facilitates Verilog design and simulation of a prototype SoC based on the Cortex-M0 DesignStart processor. To access this kit, you need to register interest. The DesignStart Design Kit comes with a free license giving 3 months use of the Keil MDK software development tools.

Both the DesignStart Design Kit and the FPGA Prototyping Kit come with Testbenches – documentation on these is available in each of the kit deliverables.

For simulation purposes, the DesignStart FPGA Prototyping Testbench requires access to the obfuscated, but synthesizable, Verilog version of the Cortex-M0 processor from the DesignStart Design Kit.

For software testing on FPGA hardware, the MPS2 platform supports debug connection to software development environments like Keil MDK. MPS2 firmware supports CMSIS-DAP so you can connect a debugger to the Cortex-M0 in the FPGA with the USB connection on the MPS2 board. When the obfuscated code for the Cortex-M0 core has been downloaded and installed, you can compile standard C code for the Cortex-M0 processor from DesignStart to exercise both the internal FPGA peripherals and also the external MPS2 peripherals.

To download a program image to the FPGA board, the debug configuration needs to setup program download options as (in Keil MDK):

Figure 4: Keil MDK Debug Configuration setup

You will see a warning message when starting a Keil MDK debug session saying "No flash Operation selected".  This is okay and can be ignored.

The documentation provided with the kits describes the systems in more detail, and explains the differences in structure and connectivity between the two kits. This might be important when source code that might have been developed using the DesignStart Design Kit is applied to the FPGA Prototyping Kit for simulation and testing.

Once ready for manufacturing, a “Fast Track” license agreement offers the licensee rights to manufacture the Cortex-M0 based device through a low-cost, standardized license agreement.

Find out further information on accessing the free DesignStart Cortex-M0 and the Fast Track License below.

More information on DesignStart