As we move to an era where intelligence and connectivity is required for even the simplest of products, there is an increased demand for custom SoCs. The Cortex-M0 is a proven baseline for these designs, where functionality must be matched against demanding cost and power efficiency constraints.This webinar will detail the Cortex-M0 processor’s features and technical specifications in the context of IoT. Additionally, it will present the latest details of ARM’s DesignStart program.
Can you really get an ARM Cortex-M0 core for design and simulation for free? Is it really possible to get to a test chip for less than $200k? Yes! Attend to learn how.
Q: How does ETM power domain link to the CORE power state? Does ITM includes in the ETM power domain? A: ETM (embedded trace macrocell) and ITM (instrumentation trace macrocell) are not part of the Cortex-M0 processor. They are available as optional blocks in Cortex-M3, Cortex-M4, and Cortex-M7. Typically, the trace blocks are put in the same power domain as the processor core.
Q: If at all, which RTOS would be supported on the Cortex-M0 core?
A: There are several ARM partner RTOS suppliers for Cortex-M, for example, FreeRTOS as well as ARM’s own Keil RTX.
Q: Is there a CoreMark for the Cortex-M23?
A: The target Coremark score for Cortex-M23 is 2.50 Coremarks/MHz. Official resultshttp://www.eembc.org/coremark/index.phpwill become available when devices based on Cortex-M23 become available on the market.
Q: Is GLOBALFOUNDRIES 22FDX platform available with ARM Cortex-M0 DesignStart?
A: The Cortex-M0 DesignStart is a package of synthesizable RTL, so it is not tied to any specific foundry or process. Please note, though, that the DesignStart is a free to design and develop only, and not suitable for taping out silicon.
Q: It is suitable for RTL system design and simulation.
A: Once ready for tape-out in your choice of foundry/process, you need a ‘fast-track’ ($40k) license agreement.
Q: You said GCC is compatible, so can I use my own library developed with gcc for ATMEGA32?
A: Please contact Microchip for information on gcc support for their ATMega product line, which is not based on Cortex-M processors. Microchip also offers the SMART microcontroller product line based on Cortex-M family of processors. gcc supports Cortex-M processors.
Q: At what frequency can we do a multiply in a single cycle at 28 um?
A: The Cortex-M0 has a configurable multiplier (fast 1-cycle, or small 32-cycles). The multiply frequency clock will depend on the implementation frequency reached.
Q: Can you elaborate what is offered in the "free" design offering? Is this intended for software development, or for hardware design RTL and DV (such as, is a Cortex-M0 DSM offered for "free"?)
A: The Cortex-M0 DesignStart is free for design and evaluation (RTL simulation). Not suitable for software development. The Cortex-M0 DesignStart is not a DSM, but actual RTL. More details on what is included in Cortex-M0 DesignStart can be found in this white paper.
Q: How could we purchase the ARM supplied FPGA to prototype? A: More information available on Arm Developer.
Q: I thought the Cortex-M1 was the only core optimized for FPGA - is it possible to have the Cortex-M0 for FPGA in production?A: Since the Cortex-M0 is fully synthesizable RTL, it can be targeted at FPGA implementation as well. However, the Cortex-M1 has been optimized specifically for FPGA implementation.
Q: Can we develop our own RTL code around the Cortex-M0 on the FPGA to prototype our own SoC?
A: Yes. The Cortex-M0 DesignStart FPGA prototyping kit supports partial reconfiguration, which allows for custom logic to be implemented around the Cortex-M0 processor on the same FPGA. More information can be found in this white paper under the section “What is the Cortex-M0 DesignStart FPGA Prototyping Kit?”.
Q: Can we use our own custom FPGA board as a target?
A: The Cortex-M0 DesignStart FPGA prototyping image is only supported by ARM’s MPS2 board.
Q: In the free evaulation, can we generate GDSII with our particular ASIC flow?
A:The Cortex-M0 DesignStart free evaluation is RTL, so yes, it can be put through your flow to generate GDSII. That said, the RTL is flattened without possibility for the tool to carry out hierarchical optimizations, so the implementation will not be optimal.
For area/power full implementation evaluations we would recommend you access the standard (not ‘DesignStart’) Cortex-M0 RTL package. Details of the Cortex-M0 DesignStart package can be found in this white paper.
Q: Is the M0 available with Fast Models?
A: All Cortex-M processors are available with Fast Models.