Agnisys, Inc. was formed in 2007 in Massachusetts USA, by industry leaders having more than two decades of experience in EDA and IT field. Agnisys builds innovate products that solve complex design and verification problems. It has R&D centers in India and USA with a creative team of more than 20 engineers. Agnisys has established itself as leading Electronic Design Automation (EDA) supplier with more than 500 users worldwide. Its products use patented technology and provides institutive user interfaces with high-end technology underneath. As a result, Agnisys’ products are now de-facto standards in many industry verticals e.g. Defense and Avionics.
Our vision is to enable chip development teams complete their projects faster with high efficiency and quality.
Our mission is to provide Specification Driven chip development products to semiconductor teams.
Industry Partnership & Association
We are a leading contributor to Accellera – the global industry consortium, for the latest advancement of SystemRDL, IP-XACT, UVM, SystemC, UVM-SystemC, CCI, standards for last three years.
We partner with leading EDA companies like Mentor Graphics, Synopsys, Cadence, Aldec etc. so that our common customers get a smooth flow between our and the other vendor tools. Last year we signed OEM partnership with OneSpin to harness the OneSpin formal verification technology as an extension to the register verification.
IDesignSpec™ - IDesignSpec is Agnisys’ flagship award winning product that allows an IP, chip or system designers to create the register map specification for their digital system once and automatically generate all of the required outputs from it. It helps create peripherals for AMBA buses such as AXI, AHB, APB and others such as OCP-IP, MIPI etc.
A wide range of outputs are generated such as UVM, OVM, RALF, SystemRDL, IP-XACT and user defined outputs created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.
ARV-Formal™ is takes the register specification and RTL design as input and performs formal proof to ensure all register operations conform to the specification. ARV-Formal is powered by an embedded version of (OneSpin 360® DV Verify) to provide a one-button seamless process flow leveraging the power of modern formal verification tools. ARV-Formal automatically generates assertions directly from the specification therefore completely automating setup and ensuring a very rapid return on investment.
ARV-Sim™ is a register verification solution that integrates with Synopsys VCS®, Cadence Incisive® and Mentor Questa® simulators. ARV-Sim automatically generates the complete package required for System Verilog (SV), Universal Verification Methodology (UVM) based testing. This approach eliminates the lengthy and error prone UVM test bench and sequence creation process. ARV-Sim provides the positive and negative sequences automatically – not just the test bench but also the actual test sequences that stimulates the hardware to ensure that the implementation is correct.
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