• State Accepted Answer
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 4 replies
  • Subscribers 348 subscribers
  • Views 6450 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

L2 Cache(Pl310) initialisation sequence

Shravan Alugala

Hi ,

I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core.

Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn't see any Drhit,Dwhit event count register gets updated.

Kindly let me know to Observe the Event Counter register does MMU initialisation required ?   or the initialisation sequence is wrong .

{ no format }
l2_cache_init:
        
        MRC p15, 0, r0, c1, c0, 0 ;@ Read System Control Register
        ORR r0, r0, #(0x1 << 12) ;@ Set I bit 12 to enable I Cache
        ORR r0, r0, #(0x1 << 2) ;@ Set C bit 2 to enable D Cache
        ORR r0, r0, #(0x1 << 11) ;@ Set Z bit 11 to enable branch prediction
        MCR p15, 0, r0, c1, c0, 0 ;@ Write System Control Register
        ldr r0,L2CC_PL310
        @ Set aux cntrl
        @ Way size = 64KB
        ldr     r1, =0x31160000
        str     r1, [r0,#0x104]
        @ Set tag RAM latency
        @ 8 cycles RAM write access latency
        @ 8 cycles RAM read access latency
        @ 8 cycles RAM setup latency
        ldr     r1, =0x00000777
        str     r1, [r0,#0x108]
        @ Set Data RAM latency
        @ 8 cycles RAM write access latency
        @ 8 cycles RAM read access latency
        @ 8 cycles RAM setup latency
        ldr     r1, =0x00000777
        str     r1, [r0,#0x10C]
        @Cache maintenance - invalidate by way (0xff) - base offset 0x77C
        ldr     r1, =0xFF
        str     r1, [r0,#0x77C]
poll_invalidate:
        ldr     r1, [r0,#0x77C]
        tst     r1, #1
        bne     poll_invalidate
        @ Enable Event Counter Control Register. Reset counter 0 and 1 values
        ldr     r1, =0x007
        str     r1, [r0,#0x200]
 @ Counter 1. Count Drhit event
        LDR     r1, =0x008
        STR     r1, [r0,#0x204]
@ Counter 0. Count Dwhit event
        LDR     r1, =0x010
        STR     r1, [r0,#0x208]
        @ Ensure L2 remains Enabled
        LDR     r1, =0x1
        STR     r1, [r0,#0x100]
        mov     pc, lr
 
L2CC_PL310:
             .word   0xD46F4000
{no format}
Parents Reply Children
No data