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MBERROR : AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave

Hi,

Facing the issue:
"MBERROR : AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave"

Here is the Inputs:

We are using the custom SOC, in which we are testing the CLCD controller(IP ARM PL111)
connected the TFT LCD 24 Bit mode on the Board , Configured the PL111 Registers based on the LCD.
(Base address of CLCD : 0xD4554000) (LCD Resolution: 800X480)

Dump of the Registers:
Address: d4554000        Value of tim0 REG: 0x2ed228c4
Address: d4554004        Value of tim1 REG: 0x171851df
Address: d4554008        Value of tim2 REG: 0x31f000a
Address: d455400c        Value of tim3 REG: 0x10000
Address: d4554010        Value of ubas REG: 0x3fed6000
Address: d4554014        Value of lbas REG: 0x0
Address: d4554018        Value of cntl REG: 0x1092b
Address: d4554020        Value of stat REG: 0x14
Address: d4554024        Value of intr REG: 0x0
Address: d4554028        Value of ucur REG: 0x0
Address: d455402c        Value of lcur REG: 0x3fed6000
Address: d4554200        Value of palette REG: 0x4a93b220
Address: d4554800        Value of crsrimg REG: 0x20518640
Address: d4554c00        Value of crsrctrl REG: 0x0
Address: d4554c04        Value of crsrcnfg REG: 0x0
Address: d4554c08        Value of crsrplte0 REG: 0x0
Address: d4554c0c        Value of crsrplte1 REG: 0x0
Address: d4554c14        Value of crsrclip REG: 0x0

Raw Interrupt Status Register Value: 0x14

Name    Baseoffset    Type    Reset value    Description
LCDRIS   0x020        RO    0x0        Raw Interrupt Status Register

In "LCDRIS" Register, MBERROR(bit 5) is set

Technical Reference Manual of PL111 Says:
MBERROR : AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave.

Please help out to resolve the issue.

Regards,
Ratan

Top replies

Colin Campbell over 6 years ago +1 suggested

Hello Ratan, As you have worked out the MBERROR message indicates that the PL111 AHB Master has received a bus error response from a slave, what slave was being accessed at the time this response was...

0 Carl Williamson over 6 years ago

Hi Ratan, I've moved your question to the SoC Design Community where I think you will get your anwser.
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+1 Colin Campbell over 6 years ago

Hello Ratan,

As you have worked out the MBERROR message indicates that the PL111 AHB Master has received a bus error response from a slave, what slave was being accessed at the time this response was received ?

Why did that slave return an error ?

As this is a custom SOC there won't be any generic answer to give you, it will depend almost totally on the SOC implementation, and the SOC designers would be the best source of help for you.

Regards,

Colin
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0 Logicallyfit over 6 years ago in reply to Colin Campbell

Hi Ratan,

As Campbell has rightly pointed out, in custom SoC it is best to look at the source design.

Some possible AHB slave errors are

1. Trying to write onto a read only slave register space, and vice versa

2. Trying to access an undefined address space in the slave.Address the master accesses may lie within the slave address range but it is quite possible that there are no registers defined for that address in the slave.
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