Hello Axi experts,
I am facing confusion in how is the below axi transcation with unaligned address converted from axi3/4 to axi lite?
Axi3 DataBus Width = 64
Axi Lite Data Bus Width = 32
For this specific example the main issue is that the 64-bit unaligned start address is actually 32-bit aligned, so the downsizing from 64-bits to 32-bits SHOULD recognise this and only produce an 8-beat FIXED transaction to the 32-bit aligned 0x4864cc address.
Then the subsequent 32-bit data bus AXI-lite protocol conversion is simply 8 transactions all to the same FIXED (aligned) address.
The complexity here seems to be more how the data width downsizing functions, rather than the protocol conversion to AXI-lite, so were you thinking of any other way the data width downsizing could have been implemented that might have resulted in more complexity for the AXI-lite protocol conversion ?
Thanks for clarifying. I agree that complexity is in the downsizing functions. Actually the designer of this converter was generating 2 transactions per beat in this case too. Since the Spec does not clearly mention unaligned fixed burst conversion case, so i though of asking an expert before taking it back to designer to fix rtl.