Axi read fixed burst with unaligned address

Hello Axi experts,

I am facing confusion in how is the below axi transcation with unaligned address converted from axi3/4 to axi lite?

Axi3 DataBus Width = 64

Axi Lite Data Bus Width = 32

The axi transaction @ Axi3 SLave interface is - 
Size       = 8
Length   = 8 beats
Address = 4864cc
kind       = Read/Write
burst      = fixed
When the burst is fixed, the address on each beat remains the same. In case INCR unaligned address, 2nd beat onwards the address is aligned. 
Question is - what is the expected conversion of address in the above case from axi3 to axiLite?
Could you please help me clearing my confusion.
Thanks
Parents
  • For this specific example the main issue is that the 64-bit unaligned start address is actually 32-bit aligned, so the downsizing from 64-bits to 32-bits SHOULD recognise this and only produce an 8-beat FIXED transaction to the 32-bit aligned 0x4864cc address.

    Then the subsequent 32-bit data bus AXI-lite protocol conversion is simply 8 transactions all to the same FIXED (aligned) address.

    The complexity here seems to be more how the data width downsizing functions, rather than the protocol conversion to AXI-lite, so were you thinking of any other way the data width downsizing could have been implemented that might have resulted in more complexity for the AXI-lite protocol conversion ?

Reply
  • For this specific example the main issue is that the 64-bit unaligned start address is actually 32-bit aligned, so the downsizing from 64-bits to 32-bits SHOULD recognise this and only produce an 8-beat FIXED transaction to the 32-bit aligned 0x4864cc address.

    Then the subsequent 32-bit data bus AXI-lite protocol conversion is simply 8 transactions all to the same FIXED (aligned) address.

    The complexity here seems to be more how the data width downsizing functions, rather than the protocol conversion to AXI-lite, so were you thinking of any other way the data width downsizing could have been implemented that might have resulted in more complexity for the AXI-lite protocol conversion ?

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