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Narrow burst (32 bit read) on a 64 bit data bus AXI read transaction

VijeyShankar

Hello All,

  I have a 64 bit data bus and I am making a 32 bit INCR with length 4(INCR4) write on it by giving the starting address.

When  I read back at the same address, I am getting as 2 64 bit data each for 2 clock cycles. Why is this?

Scenario : Single master single slave only.

Example: I write 32 bit data from 9000_0000 on INCR4. Data is stored at 9000_0000,9000_0004, 9000_0008,9000_000C. INCR4 address as calculated by slave.

D1 to D4 are all 32 bit data.

9000_0000 ---- D1

9000_0004 ----- D2

9000_0008 ----- D3

9000_000C ------ D4

When I read at 9000_0000 with INCR4, I am getting output as 

1st clk  ----  D2 D1

2nd clk ---- D2 D1

3rd clk  ---- D4 D3

4th ck  -----  D4 D3

Question: When I read at 9000_0000, my slave also calculates address in terms of 32 bit only, so why should I not expect the following:

1st clk --- D2 D1

2nd clk --- D3 D2

3rd clk  ---- D4 D3

4th clk ----- RA D4

RA -- stores for random data that is present in the next address. 

Question: When data is being read from memory, why is my data being read twice and not continuous?

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  • 0

    Hi Vijey,

    As per AXI protocol whatever behavior you are getting is correct. In your case, AXI has 64bit data width and you are trying to read the data. so AXI slave will read the 64bit data from memory in single clock and pass it to the interface. Now it's master responsibily to take valid data from 64bit.
    Now come to your point why not having D2-D1, D3-D2, D4-D3 ... , in AXI, addresses always alighed to the data width. for example, if you are writing the 32bit data on axi bus with address 0x0 onwords, you will get this type of sequence on write data channel in waverorm,

    CLK    ADDR    DATA

    1st       0x0       XX-D1
    2nd      0x4       D2-XX
    3rd       0x8      XX-D3
    4rd       0xC      D4-XX

    If you are not seeing this type of sequence that Master is not sending write data as per AXI protocol.
    Always, data width lanes are aligned to addresses and data also should be placed on proper lanes. Even for read case, slave needs only one clock cycle to read the 64bit data and give it to master for two clock cycle with appropriate byte lanes.
    You may also refer narrow transfer section in AXI-ACE specification with "A3.4.3".

    Hope it helps.

    -Vishal S

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  • 0

    Hi Vijey,

    As per AXI protocol whatever behavior you are getting is correct. In your case, AXI has 64bit data width and you are trying to read the data. so AXI slave will read the 64bit data from memory in single clock and pass it to the interface. Now it's master responsibily to take valid data from 64bit.
    Now come to your point why not having D2-D1, D3-D2, D4-D3 ... , in AXI, addresses always alighed to the data width. for example, if you are writing the 32bit data on axi bus with address 0x0 onwords, you will get this type of sequence on write data channel in waverorm,

    CLK    ADDR    DATA

    1st       0x0       XX-D1
    2nd      0x4       D2-XX
    3rd       0x8      XX-D3
    4rd       0xC      D4-XX

    If you are not seeing this type of sequence that Master is not sending write data as per AXI protocol.
    Always, data width lanes are aligned to addresses and data also should be placed on proper lanes. Even for read case, slave needs only one clock cycle to read the 64bit data and give it to master for two clock cycle with appropriate byte lanes.
    You may also refer narrow transfer section in AXI-ACE specification with "A3.4.3".

    Hope it helps.

    -Vishal S

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