This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

cortex-a7的cache配置

大家好,我自己开发基于cortex-a7 4核的SMP模式OS。采用短描述符(Short-descriptor format memory region attributes)
配置现某段内存,其TLB表项的Memory region attributes配置为:
 -----------+-----+----+
|TEX[2:0]   |  C  |  B |
+-----------+-----+----+
| 1  0 1    |  0  | 1  |
+-----------+-----+----+
意思是:
  Inner Write-Back Write Allocate, Outer Write-Back Write Allocate, Shareability determined by [S] bit

上述配置在多cpu工作时出现问题,例如,cpu3对变量进行修改,在cpu1访问该变量时却发现变量的值没有改变
只有将TLB表项配置为:Inner Write-Through, Outer Write-Back Write Allocate
 -----------+-----+----+
|TEX[2:0]   |  C  |  B |
+-----------+-----+----+
| 1  1 0    |  1  | 0  |
+-----------+-----+----+
才工作正常,后来发现需要配置内部写直通模式(Inner Write-Through)才可以,要么在cpu1访问有关变量时,执行cache invalidate
希望专家解答