请教一下,ARM MPcore系统中ACP(加速器一致性接口的 )作用,具体应用场景?如何配置?

如题,ARM MPcore系统中ACP(加速器一致性接口的 )作用,具体应用场景?如何配置?

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  • What is ACP?

    Most of ARM's MPCore processors include an ACP, or Accelerator Coherency Port.  ACPs are just AXI slave ports.  You can connect an AXI master to the port, and the transactions generated by that master will pass through the MPCore processor in order to reach the main memory system.

    Why?

    This is  a way of taking a non-cache coherent master and making it cache coherent.

    As the master's transactions pass through the processor, they are visible to the coherency logic in the processor.  This means that should they access an address held in the processor's caches, it can take the necessary steps to ensure coherency. Exactly how this works is down to the specific MPCore processor.

    Note: In practice, it would have to be a non-cached master.  As the ACP only gives visibility of the bus transactions, not any up-stream caches.

    Who initiates transactions over ACP?

    The master (the thing you connected to the ACP). From its perspective not much has changed.

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