architecture: aarch64, flags 0x00000112: EXEC_P, HAS_SYMS, D_PAGED start address 0x0000000000000000 Program Header: LOAD off 0x0000000000010000 vaddr 0x0000000000000000 paddr 0x0000000000000000 align 2**16 filesz 0x000000000000a048 memsz 0x000000000000f0c0 flags rwx NOTE off 0x0000000000011674 vaddr 0x0000000000001674 paddr 0x0000000000001674 align 2**2 filesz 0x0000000000000024 memsz 0x0000000000000024 flags r-- private flags = 0: Sections: Idx Name Size VMA LMA File off Algn 0 .text 000015ec 0000000000000000 0000000000000000 00010000 2**8 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .init 00000034 0000000000001600 0000000000001600 00011600 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .fini 00000034 0000000000001640 0000000000001640 00011640 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 3 .note.gnu.build-id 00000024 0000000000001674 0000000000001674 00011674 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .rodata 000000a8 0000000000001698 0000000000001698 00011698 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .rodata1 00000000 0000000000001740 000000000000a048 0001a048 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .sdata2 00000000 0000000000001740 0000000000001740 0001a048 2**0 CONTENTS 7 .sbss2 00000000 0000000000001740 0000000000001740 0001a048 2**0 CONTENTS 8 .data 000008e0 0000000000001740 0000000000001740 00011740 2**3 CONTENTS, ALLOC, LOAD, DATA 9 .data1 00000020 0000000000002020 0000000000002020 00012020 2**0 ALLOC 10 .ctors 00000000 0000000000002040 0000000000002040 0001a048 2**0 CONTENTS 11 .dtors 00000000 0000000000002040 0000000000002040 0001a048 2**0 CONTENTS 12 .eh_frame 00000004 0000000000002040 0000000000002040 00012040 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 13 .mmu_tbl0 00000010 0000000000003000 0000000000003000 00013000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 14 .mmu_tbl1 00002000 0000000000004000 0000000000004000 00014000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 15 .mmu_tbl2 00004000 0000000000006000 0000000000006000 00016000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 16 .preinit_array 00000000 000000000000a000 000000000000a048 0001a048 2**0 CONTENTS, ALLOC, LOAD, DATA 17 .init_array 00000008 000000000000a000 000000000000a000 0001a000 2**3 CONTENTS, ALLOC, LOAD, DATA 18 .fini_array 00000040 000000000000a008 000000000000a008 0001a008 2**3 CONTENTS, ALLOC, LOAD, DATA 19 .sdata 00000038 000000000000a048 000000000000a048 0001a048 2**0 ALLOC 20 .sbss 00000000 000000000000a080 000000000000a080 0001a048 2**0 CONTENTS 21 .tdata 00000000 000000000000a080 000000000000a080 0001a048 2**0 CONTENTS, ALLOC, LOAD, DATA, THREAD_LOCAL 22 .tbss 00000000 000000000000a080 000000000000a080 00000000 2**0 ALLOC, THREAD_LOCAL 23 .bss 00000040 000000000000a080 000000000000a080 0001a048 2**3 ALLOC 24 .heap 00002000 000000000000a0c0 000000000000a0c0 0001a048 2**0 ALLOC 25 .stack 00003000 000000000000c0c0 000000000000c0c0 0001a048 2**0 ALLOC 26 .comment 00000031 0000000000000000 0000000000000000 0001a048 2**0 CONTENTS, READONLY 27 .debug_line 000016cd 0000000000000000 0000000000000000 0001a079 2**0 CONTENTS, READONLY, DEBUGGING 28 .debug_info 00003082 0000000000000000 0000000000000000 0001b746 2**0 CONTENTS, READONLY, DEBUGGING 29 .debug_abbrev 00000bc4 0000000000000000 0000000000000000 0001e7c8 2**0 CONTENTS, READONLY, DEBUGGING 30 .debug_aranges 00000270 0000000000000000 0000000000000000 0001f390 2**4 CONTENTS, READONLY, DEBUGGING 31 .debug_str 00011a5d 0000000000000000 0000000000000000 0001f600 2**0 CONTENTS, READONLY, DEBUGGING 32 .debug_macro 00003acb 0000000000000000 0000000000000000 0003105d 2**0 CONTENTS, READONLY, DEBUGGING 33 .debug_frame 00000318 0000000000000000 0000000000000000 00034b28 2**3 CONTENTS, READONLY, DEBUGGING 34 .debug_loc 000006e1 0000000000000000 0000000000000000 00034e40 2**0 CONTENTS, READONLY, DEBUGGING 35 .debug_ranges 000000c0 0000000000000000 0000000000000000 00035521 2**0 CONTENTS, READONLY, DEBUGGING SYMBOL TABLE: 0000000000000000 l d .text 0000000000000000 .text 0000000000001600 l d .init 0000000000000000 .init 0000000000001640 l d .fini 0000000000000000 .fini 0000000000001674 l d .note.gnu.build-id 0000000000000000 .note.gnu.build-id 0000000000001698 l d .rodata 0000000000000000 .rodata 0000000000001740 l d .rodata1 0000000000000000 .rodata1 0000000000001740 l d .sdata2 0000000000000000 .sdata2 0000000000001740 l d .sbss2 0000000000000000 .sbss2 0000000000001740 l d .data 0000000000000000 .data 0000000000002020 l d .data1 0000000000000000 .data1 0000000000002040 l d .ctors 0000000000000000 .ctors 0000000000002040 l d .dtors 0000000000000000 .dtors 0000000000002040 l d .eh_frame 0000000000000000 .eh_frame 0000000000003000 l d .mmu_tbl0 0000000000000000 .mmu_tbl0 0000000000004000 l d .mmu_tbl1 0000000000000000 .mmu_tbl1 0000000000006000 l d .mmu_tbl2 0000000000000000 .mmu_tbl2 000000000000a000 l d .preinit_array 0000000000000000 .preinit_array 000000000000a000 l d .init_array 0000000000000000 .init_array 000000000000a008 l d .fini_array 0000000000000000 .fini_array 000000000000a048 l d .sdata 0000000000000000 .sdata 000000000000a080 l d .sbss 0000000000000000 .sbss 000000000000a080 l d .tdata 0000000000000000 .tdata 000000000000a080 l d .tbss 0000000000000000 .tbss 000000000000a080 l d .bss 0000000000000000 .bss 000000000000a0c0 l d .heap 0000000000000000 .heap 000000000000c0c0 l d .stack 0000000000000000 .stack 0000000000000000 l d .comment 0000000000000000 .comment 0000000000000000 l d .debug_line 0000000000000000 .debug_line 0000000000000000 l d .debug_info 0000000000000000 .debug_info 0000000000000000 l d .debug_abbrev 0000000000000000 .debug_abbrev 0000000000000000 l d .debug_aranges 0000000000000000 .debug_aranges 0000000000000000 l d .debug_str 0000000000000000 .debug_str 0000000000000000 l d .debug_macro 0000000000000000 .debug_macro 0000000000000000 l d .debug_frame 0000000000000000 .debug_frame 0000000000000000 l d .debug_loc 0000000000000000 .debug_loc 0000000000000000 l d .debug_ranges 0000000000000000 .debug_ranges 0000000000000000 l df *ABS* 0000000000000000 asm_vectors.o 0000000000000210 l *ABS* 0000000000000000 FPUContextSize 0000000000000000 l .text 0000000000000000 VBAR 0000000000000384 l .text 0000000000000000 SynchronousInterruptHandler 0000000000000488 l .text 0000000000000000 IRQInterruptHandler 0000000000000584 l .text 0000000000000000 FIQInterruptHandler 00000000000005e4 l .text 0000000000000000 SErrorInterruptHandler 0000000000000454 l .text 0000000000000000 synchronoushandler 00000000000003f8 l .text 0000000000000000 storefloat 0000000000000700 l .text 0000000000000000 FPUContext 0000000000000910 l .text 0000000000000000 FPUContextBase 0000000000000458 l .text 0000000000000000 restorecontext 0000000000000540 l .text 0000000000000000 RestorePrevState 0000000000000000 l df *ABS* 0000000000000000 boot.o 0000000000000000 l *ABS* 0000000000000000 TT_S1_FAULT 0000000000000003 l *ABS* 0000000000000000 TT_S1_TABLE 00000000fd5c0040 l *ABS* 0000000000000000 rvbar_base 0000000005f5b9f5 l *ABS* 0000000000000000 counterfreq 0000000000000005 l *ABS* 0000000000000000 MODE_EL1 00000000000001c0 l *ABS* 0000000000000000 DAIF_BIT 00000000000009b4 l .text 0000000000000000 OKToRun 00000000000009cc l .text 0000000000000000 InitEL3 0000000000000ab4 l .text 0000000000000000 InitEL1 0000000000000ab8 l .text 0000000000000000 error 0000000000000abc l .text 0000000000000000 invalidate_dcaches 0000000000000b44 l .text 0000000000000000 invalidateCaches_end 0000000000000ad4 l .text 0000000000000000 invalidateCaches_flush_level 0000000000000b38 l .text 0000000000000000 invalidateCaches_next_level 0000000000000b0c l .text 0000000000000000 invalidateCaches_flush_set 0000000000000b10 l .text 0000000000000000 invalidateCaches_flush_way 0000000000000000 l df *ABS* 0000000000000000 /proj/xbuilds/2018.3_0916_1956/installs/lin64/SDK/2018.3/gnu/aarch64/lin/aarch64-none/bin/../lib/gcc/aarch64-none-elf/7.3.1/crti.o 0000000000000000 l df *ABS* 0000000000000000 crtstuff.c 0000000000002040 l O .eh_frame 0000000000000000 0000000000000b90 l F .text 0000000000000000 deregister_tm_clones 0000000000000bc0 l F .text 0000000000000000 register_tm_clones 0000000000000bf8 l F .text 0000000000000000 __do_global_dtors_aux 000000000000a080 l O .bss 0000000000000001 completed.7089 000000000000a040 l O .fini_array 0000000000000000 __do_global_dtors_aux_fini_array_entry 0000000000000c40 l F .text 0000000000000000 frame_dummy 000000000000a088 l O .bss 0000000000000030 object.7094 000000000000a000 l O .init_array 0000000000000000 __frame_dummy_init_array_entry 0000000000000000 l df *ABS* 0000000000000000 /proj/xbuilds/2018.3_0916_1956/installs/lin64/SDK/2018.3/gnu/aarch64/lin/aarch64-none/bin/../aarch64-none-elf/libc/usr/lib/crt0.o 0000000000001748 l .data 0000000000000000 HeapBase 0000000000001768 l .data 0000000000000000 env 0000000000001770 l .data 0000000000000000 CommandLine 0000000000001758 l .data 0000000000000000 StackBase 0000000000001750 l .data 0000000000000000 HeapLimit 0000000000001760 l .data 0000000000000000 StackLimit 0000000000000000 l df *ABS* 0000000000000000 helloworld.c 0000000000000000 l df *ABS* 0000000000000000 platform.c 0000000000000000 l df *ABS* 0000000000000000 initialise_monitor_handles.c 0000000000000000 l df *ABS* 0000000000000000 print.c 0000000000000000 l df *ABS* 0000000000000000 translation_table.o 0000000000000000 l *ABS* 0000000000000000 reserved 0000000000000705 l *ABS* 0000000000000000 Memory 0060000000000409 l *ABS* 0000000000000000 Device 00000000ffe00000 l *ABS* 0000000000000000 SECT 0000000800000000 l *ABS* 0000000000000000 DDR_1_START 000000087fffffff l *ABS* 0000000000000000 DDR_1_END 0000000080000000 l *ABS* 0000000000000000 DDR_1_SIZE 0000000000000002 l *ABS* 0000000000000000 DDR_1_REG 000000000000001e l *ABS* 0000000000000000 UNDEF_1_REG 0000000000000000 l *ABS* 0000000000000000 DDR_0_START 000000007fffffff l *ABS* 0000000000000000 DDR_0_END 0000000080000000 l *ABS* 0000000000000000 DDR_0_SIZE 0000000000000400 l *ABS* 0000000000000000 DDR_0_REG 0000000000000000 l *ABS* 0000000000000000 UNDEF_0_REG 0000000000000000 l df *ABS* 0000000000000000 vectors.c 0000000000000000 l df *ABS* 0000000000000000 xil-crt0.S 00000000fd5c0090 l *ABS* 0000000000000000 APU_PWRCTL 0000000000000000 l df *ABS* 0000000000000000 xil_exception.c 0000000000000f30 l F .text 0000000000000004 Xil_ExceptionNullHandler 0000000000000000 l df *ABS* 0000000000000000 outbyte.c 0000000000000000 l df *ABS* 0000000000000000 xuartps_hw.c 0000000000000000 l df *ABS* 0000000000000000 atexit.c 0000000000000000 l df *ABS* 0000000000000000 exit.c 0000000000000000 l df *ABS* 0000000000000000 fini.c 0000000000000000 l df *ABS* 0000000000000000 impure.c 00000000000018d8 l O .data 0000000000000748 impure_data 0000000000000000 l df *ABS* 0000000000000000 init.c 0000000000000000 l df *ABS* 0000000000000000 lib_a-memset.o 0000000000000000 l df *ABS* 0000000000000000 __atexit.c 0000000000000000 l df *ABS* 0000000000000000 __call_atexit.c 0000000000000000 l df *ABS* 0000000000000000 _exit.c 0000000000000000 l df *ABS* 0000000000000000 crtstuff.c 0000000000002040 l O .eh_frame 0000000000000000 __FRAME_END__ 0000000000000000 l df *ABS* 0000000000000000 /proj/xbuilds/2018.3_0916_1956/installs/lin64/SDK/2018.3/gnu/aarch64/lin/aarch64-none/bin/../lib/gcc/aarch64-none-elf/7.3.1/crtn.o 000000000000e4c0 g .stack 0000000000000000 _el1_stack_end 0000000000006000 g .mmu_tbl2 0000000000000000 __mmu_tbl2_start 0000000000000e78 g F .text 0000000000000010 SynchronousInterrupt 0000000000000000 g .text 0000000000000000 _vector_table 0000000000002044 g .eh_frame 0000000000000000 __eh_framehdr_start 0000000000002040 g .ctors 0000000000000000 ___CTORS_LIST___ 0000000000000e28 g F .text 0000000000000030 print 0000000000000400 g *ABS* 0000000000000000 _EL2_STACK_SIZE 0000000000000400 g *ABS* 0000000000000000 _EL0_STACK_SIZE 0000000000000e20 w F .text 0000000000000004 initialise_monitor_handles 0000000000000dd0 g F .text 0000000000000008 enable_caches 000000000000a000 g .mmu_tbl2 0000000000000000 __exidx_end 0000000000000fd0 g F .text 000000000000001c XUartPs_SendByte 0000000000000f48 g F .text 0000000000000004 Xil_ExceptionInit 000000000000a080 g .sbss 0000000000000000 __sbss_start 0000000000000ff0 g F .text 000000000000001c XUartPs_RecvByte 000000000000e4c0 g .stack 0000000000000000 __el2_stack 000000000000e0c0 g .stack 0000000000000000 _el2_stack_end 0000000000002040 g .dtors 0000000000000000 __fixup_start 0000000000000938 g .text 0000000000000000 _boot 0000000000002040 g .dtors 0000000000000000 __fixup_end 0000000000002020 g O .data 0000000000000000 .hidden __TMC_END__ 000000000000a080 g .sdata 0000000000000000 __sdata_start 0000000000003010 g .mmu_tbl0 0000000000000000 __mmu_tbl0_end 0000000000002040 g .dtors 0000000000000000 __DTOR_END__ 0000000000000de8 g F .text 000000000000001c init_platform 000000000000a048 g .fini_array 0000000000000000 __fini_array_end 0000000000001740 g .rodata 0000000000000000 __rodata_end 0000000000002040 g .data1 0000000000000000 __data1_start 0000000000001740 g .sbss2 0000000000000000 __sbss2_end 000000000000a080 g .bss 0000000000000000 __bss_start__ 0000000000001740 g O .data 0000000000000000 .hidden __dso_handle 0000000000000de0 g F .text 0000000000000008 init_uart 0000000000006000 g .mmu_tbl2 0000000000000000 MMUTableL2 000000000000c0c0 g .heap 0000000000000000 _heap_end 000000000000a000 g .mmu_tbl2 0000000000000000 __exidx_start 0000000000000e68 g F .text 0000000000000010 IRQInterrupt 00000000000016d0 g O .rodata 0000000000000008 _global_impure_ptr 0000000000001118 g F .text 000000000000008c __libc_init_array 0000000000001740 g .rodata1 0000000000000000 __rodata1_start 0000000000000f38 g F .text 0000000000000004 Xil_SyncAbortHandler 0000000000000c78 g .text 0000000000000000 _mainCRTStartup 000000000000a048 g .fini_array 0000000000000000 __ARM.attributes_end 0000000000000eb8 g .text 0000000000000070 _startup 000000000000a080 g .tbss 0000000000000000 __tbss_start 0000000000001600 g F .init 0000000000000000 _init 0000000000006000 g .mmu_tbl1 0000000000000000 __mmu_tbl1_end 0000000000000f40 g F .text 0000000000000004 Xil_SErrorAbortHandler 00000000000010d0 g F .text 0000000000000044 __libc_fini_array 0000000000000f50 g F .text 000000000000001c Xil_ExceptionRegisterHandler 000000000000a0c0 g .heap 0000000000000000 _heap_start 000000000000a080 g .sbss 0000000000000000 __sbss_end 0000000000000938 g .text 0000000000000000 _prestart 0000000000001758 g .data 0000000000000000 __stack_base__ 0000000000002040 g .ctors 0000000000000000 __CTOR_LIST__ 0000000000001740 g .sbss2 0000000000000000 __sbss2_start 000000000000a0c0 g .bss 0000000000000000 __bss_end__ 000000000000c0c0 g .stack 0000000000000000 _el3_stack_end 0000000000001490 g F .text 0000000000000154 __call_exitprocs 0000000000000c78 g .text 0000000000000000 _start 00000000000016c0 g .rodata 0000000000000000 __rodata_start 000000000000a080 g *ABS* 0000000000000000 _SDA_BASE_ 0000000000001398 g F .text 00000000000000f4 __register_exitproc 0000000000002020 g .data 0000000000000000 __data_end 000000000000a0c0 g .heap 0000000000000000 HeapBase 0000000000000800 g *ABS* 0000000000000000 _EL1_STACK_SIZE 0000000000000918 g .text 0000000000000000 FPUStatus 0000000000003000 g .mmu_tbl0 0000000000000000 MMUTableL0 0000000000002044 g .eh_frame 0000000000000000 __eh_framehdr_end 0000000000000fc0 g F .text 000000000000000c outbyte 000000000000a040 g .fini_array 0000000000000000 __fini_array_start 0000000000002000 g *ABS* 0000000000000000 _STACK_SIZE 000000000000a080 g .tdata 0000000000000000 __tdata_start 000000000000a080 g .tdata 0000000000000000 __tdata_end 00000000000011c0 g F .text 00000000000001d8 memset 0000000000000da8 g F .text 0000000000000028 main 0000000000002000 g *ABS* 0000000000000000 _HEAP_SIZE 0000000000000e88 g F .text 0000000000000010 SErrorInterrupt 000000000000a008 g .init_array 0000000000000000 __init_array_end 0000000000000dd8 g F .text 0000000000000008 disable_caches 000000000000e0c0 g .stack 0000000000000000 __el3_stack 0000000000002040 g .dtors 0000000000000000 ___DTORS_END___ 000000000000a080 g .sdata 0000000000000000 __sdata_end 0000000000001740 g .sdata2 0000000000000000 __sdata2_start 0000000000002040 g .ctors 0000000000000000 __CTOR_END__ 0000000000002040 g .dtors 0000000000000000 ___DTORS_LIST___ 0000000000002040 g .dtors 0000000000000000 __DTOR_LIST__ 000000000000ecc0 g .stack 0000000000000000 _el0_stack_end 0000000000001640 g F .fini 0000000000000000 _fini 000000000000ecc0 g .stack 0000000000000000 __el1_stack 0000000000001080 g F .text 0000000000000014 atexit 00000000000018d0 g O .data 0000000000000008 _impure_ptr 000000000000a000 g .preinit_array 0000000000000000 __preinit_array_end 0000000000001740 g .sdata2 0000000000000000 __sdata2_end 000000000000f0c0 g .stack 0000000000000000 __el0_stack 0000000000001870 g O .data 0000000000000060 XExc_VectorTable 0000000000002040 g .ctors 0000000000000000 ___CTORS_END___ 000000000000c0c0 g .heap 0000000000000000 HeapLimit 0000000000000f98 g F .text 0000000000000024 Xil_ExceptionRemoveHandler 000000000000f0c0 g .stack 0000000000000000 _end 0000000000001010 g F .text 0000000000000070 XUartPs_ResetHw 0000000000001740 g .rodata1 0000000000000000 __rodata1_end 0000000000000e04 g F .text 0000000000000018 cleanup_platform 0000000000002040 g .data1 0000000000000000 __data1_end 000000000000a0c0 g .heap 0000000000000000 _heap 0000000000001098 g F .text 0000000000000034 exit 000000000000a000 g .mmu_tbl2 0000000000000000 __mmu_tbl2_end 0000000000004000 g .mmu_tbl1 0000000000000000 __mmu_tbl1_start 000000000000a080 g .tbss 0000000000000000 __tbss_end 000000000000a000 g .init_array 0000000000000000 __init_array_start 00000000000015e8 w F .text 0000000000000004 _exit 0000000000000e58 g F .text 0000000000000010 FIQInterrupt 0000000000000d6c w .text 0000000000000000 _cpu_init_hook 0000000000001740 g .data 0000000000000000 __data_start 0000000000003000 g .mmu_tbl0 0000000000000000 __mmu_tbl0_start 000000000000a000 g .preinit_array 0000000000000000 __preinit_array_start 0000000000004000 g .mmu_tbl1 0000000000000000 MMUTableL1 0000000000001740 g *ABS* 0000000000000000 _SDA2_BASE_ 0000000000000f70 g F .text 0000000000000024 Xil_GetExceptionRegisterHandler 000000000000a048 g .fini_array 0000000000000000 __ARM.attributes_start Disassembly of section .text: 0000000000000000 <_vector_table>: /* RES0 */ .dword 0 /* End of Image header. */ .endif b _boot 0: 1400024e b 938 <_boot> ... .org (VBAR + 0x200) b SynchronousInterruptHandler 200: 14000061 b 384 ... .org (VBAR + 0x280) b IRQInterruptHandler 280: 14000082 b 488 ... .org (VBAR + 0x300) b FIQInterruptHandler 300: 140000a1 b 584 ... .org (VBAR + 0x380) b SErrorInterruptHandler 380: 14000099 b 5e4 0000000000000384 : SynchronousInterruptHandler: saveregister 384: a9bf07e0 .word 0xa9bf07e0 388: a9bf0fe2 .word 0xa9bf0fe2 38c: a9bf17e4 .word 0xa9bf17e4 390: a9bf1fe6 .word 0xa9bf1fe6 394: a9bf27e8 .word 0xa9bf27e8 398: a9bf2fea .word 0xa9bf2fea 39c: a9bf37ec .word 0xa9bf37ec 3a0: a9bf3fee .word 0xa9bf3fee 3a4: a9bf47f0 .word 0xa9bf47f0 3a8: a9bf4ff2 .word 0xa9bf4ff2 3ac: a9bf7bfd .word 0xa9bf7bfd /* Check if the Synchronous abort is occured due to floating point access. */ .if (EL3 == 1) mrs x0, ESR_EL3 3b0: d53e5200 .word 0xd53e5200 .else mrs x0, ESR_EL1 .endif and x0, x0, #(0x3F << 26) 3b4: 92661400 .word 0x92661400 mov x1, #(0x7 << 26) 3b8: d2a38001 .word 0xd2a38001 cmp x0, x1 3bc: eb01001f .word 0xeb01001f /* If exception is not due to floating point access go to synchronous handler */ bne synchronoushandler 3c0: 540004a1 .word 0x540004a1 /* * If excpetion occured due to floating point access, Enable the floating point * access i.e. do not trap floating point instruction */ .if (EL3 == 1) mrs x1,CPTR_EL3 3c4: d53e1141 .word 0xd53e1141 bic x1, x1, #(0x1<<10) 3c8: 9275f821 .word 0x9275f821 msr CPTR_EL3, x1 3cc: d51e1141 .word 0xd51e1141 .else mrs x1,CPACR_EL1 orr x1, x1, #(0x1<<20) msr CPACR_EL1, x1 .endif isb 3d0: d5033fdf .word 0xd5033fdf /* If the floating point access was previously enabled, store FPU context * registers(storefloat). */ ldr x0, =FPUStatus 3d4: 58002a60 .word 0x58002a60 ldrb w1,[x0] 3d8: 39400001 .word 0x39400001 cbnz w1, storefloat 3dc: 350000e1 .word 0x350000e1 /* * If the floating point access was not enabled previously, save the status of * floating point accessibility i.e. enabled and store floating point context * array address(FPUContext) to FPUContextBase. */ mov w1, #0x1 3e0: 52800021 .word 0x52800021 strb w1, [x0] 3e4: 39000001 .word 0x39000001 ldr x0, =FPUContext 3e8: 58002a00 .word 0x58002a00 ldr x1, =FPUContextBase 3ec: 58002a21 .word 0x58002a21 str x0,[x1] 3f0: f9000020 .word 0xf9000020 b restorecontext 3f4: 14000019 .word 0x14000019 00000000000003f8 : storefloat: savefloatregister 3f8: 580029c1 .word 0x580029c1 3fc: f9400020 .word 0xf9400020 400: ac810400 .word 0xac810400 404: ac810c02 .word 0xac810c02 408: ac811404 .word 0xac811404 40c: ac811c06 .word 0xac811c06 410: ac812408 .word 0xac812408 414: ac812c0a .word 0xac812c0a 418: ac81340c .word 0xac81340c 41c: ac813c0e .word 0xac813c0e 420: ac814410 .word 0xac814410 424: ac814c12 .word 0xac814c12 428: ac815414 .word 0xac815414 42c: ac815c16 .word 0xac815c16 430: ac816418 .word 0xac816418 434: ac816c1a .word 0xac816c1a 438: ac81741c .word 0xac81741c 43c: ac817c1e .word 0xac817c1e 440: d53b4402 .word 0xd53b4402 444: d53b4423 .word 0xd53b4423 448: a8810c02 .word 0xa8810c02 44c: f9000020 .word 0xf9000020 b restorecontext 450: 14000002 .word 0x14000002 0000000000000454 : synchronoushandler: bl SynchronousInterrupt 454: 94000289 .word 0x94000289 0000000000000458 : restorecontext: restoreregister 458: a8c17bfd .word 0xa8c17bfd 45c: a8c14ff2 .word 0xa8c14ff2 460: a8c147f0 .word 0xa8c147f0 464: a8c13fee .word 0xa8c13fee 468: a8c137ec .word 0xa8c137ec 46c: a8c12fea .word 0xa8c12fea 470: a8c127e8 .word 0xa8c127e8 474: a8c11fe6 .word 0xa8c11fe6 478: a8c117e4 .word 0xa8c117e4 47c: a8c10fe2 .word 0xa8c10fe2 480: a8c107e0 .word 0xa8c107e0 eret 484: d69f03e0 .word 0xd69f03e0 0000000000000488 : IRQInterruptHandler: saveregister 488: a9bf07e0 .word 0xa9bf07e0 48c: a9bf0fe2 .word 0xa9bf0fe2 490: a9bf17e4 .word 0xa9bf17e4 494: a9bf1fe6 .word 0xa9bf1fe6 498: a9bf27e8 .word 0xa9bf27e8 49c: a9bf2fea .word 0xa9bf2fea 4a0: a9bf37ec .word 0xa9bf37ec 4a4: a9bf3fee .word 0xa9bf3fee 4a8: a9bf47f0 .word 0xa9bf47f0 4ac: a9bf4ff2 .word 0xa9bf4ff2 4b0: a9bf7bfd .word 0xa9bf7bfd /* Save the status of SPSR, ELR and CPTR to stack */ .if (EL3 == 1) mrs x0, CPTR_EL3 4b4: d53e1140 .word 0xd53e1140 mrs x1, ELR_EL3 4b8: d53e4021 .word 0xd53e4021 mrs x2, SPSR_EL3 4bc: d53e4002 .word 0xd53e4002 .else mrs x0, CPACR_EL1 mrs x1, ELR_EL1 mrs x2, SPSR_EL1 .endif stp x0, x1, [sp,#-0x10]! 4c0: a9bf07e0 .word 0xa9bf07e0 str x2, [sp,#-0x10]! 4c4: f81f0fe2 .word 0xf81f0fe2 /* Trap floating point access */ .if (EL3 == 1) mrs x1,CPTR_EL3 4c8: d53e1141 .word 0xd53e1141 orr x1, x1, #(0x1<<10) 4cc: b2760021 .word 0xb2760021 msr CPTR_EL3, x1 4d0: d51e1141 .word 0xd51e1141 .else mrs x1,CPACR_EL1 bic x1, x1, #(0x1<<20) msr CPACR_EL1, x1 .endif isb 4d4: d5033fdf .word 0xd5033fdf bl IRQInterrupt 4d8: 94000264 .word 0x94000264 * If floating point access is enabled during interrupt handling, * restore floating point registers. */ .if (EL3 == 1) mrs x0, CPTR_EL3 4dc: d53e1140 .word 0xd53e1140 ands x0, x0, #(0x1<<10) 4e0: f2760000 .word 0xf2760000 bne RestorePrevState 4e4: 540002e1 .word 0x540002e1 mrs x0,CPACR_EL1 ands x0, x0, #(0x1<<20) beq RestorePrevState .endif restorefloatregister 4e8: 58002241 .word 0x58002241 4ec: f9400020 .word 0xf9400020 4f0: a9ff0c02 .word 0xa9ff0c02 4f4: d51b4402 .word 0xd51b4402 4f8: d51b4423 .word 0xd51b4423 4fc: adff7c1e .word 0xadff7c1e 500: adff741c .word 0xadff741c 504: adff6c1a .word 0xadff6c1a 508: adff6418 .word 0xadff6418 50c: adff5c16 .word 0xadff5c16 510: adff5414 .word 0xadff5414 514: adff4c12 .word 0xadff4c12 518: adff4410 .word 0xadff4410 51c: adff3c0e .word 0xadff3c0e 520: adff340c .word 0xadff340c 524: adff2c0a .word 0xadff2c0a 528: adff2408 .word 0xadff2408 52c: adff1c06 .word 0xadff1c06 530: adff1404 .word 0xadff1404 534: adff0c02 .word 0xadff0c02 538: adff0400 .word 0xadff0400 53c: f9000020 .word 0xf9000020 0000000000000540 : /* Restore the status of SPSR, ELR and CPTR from stack */ RestorePrevState: ldr x2,[sp],0x10 540: f84107e2 .word 0xf84107e2 ldp x0, x1, [sp],0x10 544: a8c107e0 .word 0xa8c107e0 .if (EL3 == 1) msr CPTR_EL3, x0 548: d51e1140 .word 0xd51e1140 msr ELR_EL3, x1 54c: d51e4021 .word 0xd51e4021 msr SPSR_EL3, x2 550: d51e4002 .word 0xd51e4002 .else msr CPACR_EL1, x0 msr ELR_EL1, x1 msr SPSR_EL1, x2 .endif restoreregister 554: a8c17bfd .word 0xa8c17bfd 558: a8c14ff2 .word 0xa8c14ff2 55c: a8c147f0 .word 0xa8c147f0 560: a8c13fee .word 0xa8c13fee 564: a8c137ec .word 0xa8c137ec 568: a8c12fea .word 0xa8c12fea 56c: a8c127e8 .word 0xa8c127e8 570: a8c11fe6 .word 0xa8c11fe6 574: a8c117e4 .word 0xa8c117e4 578: a8c10fe2 .word 0xa8c10fe2 57c: a8c107e0 .word 0xa8c107e0 eret 580: d69f03e0 .word 0xd69f03e0 0000000000000584 : FIQInterruptHandler: saveregister 584: a9bf07e0 .word 0xa9bf07e0 588: a9bf0fe2 .word 0xa9bf0fe2 58c: a9bf17e4 .word 0xa9bf17e4 590: a9bf1fe6 .word 0xa9bf1fe6 594: a9bf27e8 .word 0xa9bf27e8 598: a9bf2fea .word 0xa9bf2fea 59c: a9bf37ec .word 0xa9bf37ec 5a0: a9bf3fee .word 0xa9bf3fee 5a4: a9bf47f0 .word 0xa9bf47f0 5a8: a9bf4ff2 .word 0xa9bf4ff2 5ac: a9bf7bfd .word 0xa9bf7bfd bl FIQInterrupt 5b0: 9400022a .word 0x9400022a restoreregister 5b4: a8c17bfd .word 0xa8c17bfd 5b8: a8c14ff2 .word 0xa8c14ff2 5bc: a8c147f0 .word 0xa8c147f0 5c0: a8c13fee .word 0xa8c13fee 5c4: a8c137ec .word 0xa8c137ec 5c8: a8c12fea .word 0xa8c12fea 5cc: a8c127e8 .word 0xa8c127e8 5d0: a8c11fe6 .word 0xa8c11fe6 5d4: a8c117e4 .word 0xa8c117e4 5d8: a8c10fe2 .word 0xa8c10fe2 5dc: a8c107e0 .word 0xa8c107e0 eret 5e0: d69f03e0 .word 0xd69f03e0 00000000000005e4 : SErrorInterruptHandler: saveregister 5e4: a9bf07e0 .word 0xa9bf07e0 5e8: a9bf0fe2 .word 0xa9bf0fe2 5ec: a9bf17e4 .word 0xa9bf17e4 5f0: a9bf1fe6 .word 0xa9bf1fe6 5f4: a9bf27e8 .word 0xa9bf27e8 5f8: a9bf2fea .word 0xa9bf2fea 5fc: a9bf37ec .word 0xa9bf37ec 600: a9bf3fee .word 0xa9bf3fee 604: a9bf47f0 .word 0xa9bf47f0 608: a9bf4ff2 .word 0xa9bf4ff2 60c: a9bf7bfd .word 0xa9bf7bfd bl SErrorInterrupt 610: 9400021e .word 0x9400021e restoreregister 614: a8c17bfd .word 0xa8c17bfd 618: a8c14ff2 .word 0xa8c14ff2 61c: a8c147f0 .word 0xa8c147f0 620: a8c13fee .word 0xa8c13fee 624: a8c137ec .word 0xa8c137ec 628: a8c12fea .word 0xa8c12fea 62c: a8c127e8 .word 0xa8c127e8 630: a8c11fe6 .word 0xa8c11fe6 634: a8c117e4 .word 0xa8c117e4 638: a8c10fe2 .word 0xa8c10fe2 63c: a8c107e0 .word 0xa8c107e0 eret 640: d69f03e0 .word 0xd69f03e0 ... 0000000000000700 : ... 0000000000000910 : ... 0000000000000918 : ... 920: 00000918 .word 0x00000918 924: 00000000 .word 0x00000000 928: 00000700 .word 0x00000700 92c: 00000000 .word 0x00000000 930: 00000910 .word 0x00000910 934: 00000000 .word 0x00000000 0000000000000938 <_boot>: /* this initializes the various processor modes */ _prestart: _boot: mov x0, #0 938: d2800000 mov x0, #0x0 // #0 mov x1, #0 93c: d2800001 mov x1, #0x0 // #0 mov x2, #0 940: d2800002 mov x2, #0x0 // #0 mov x3, #0 944: d2800003 mov x3, #0x0 // #0 mov x4, #0 948: d2800004 mov x4, #0x0 // #0 mov x5, #0 94c: d2800005 mov x5, #0x0 // #0 mov x6, #0 950: d2800006 mov x6, #0x0 // #0 mov x7, #0 954: d2800007 mov x7, #0x0 // #0 mov x8, #0 958: d2800008 mov x8, #0x0 // #0 mov x9, #0 95c: d2800009 mov x9, #0x0 // #0 mov x10, #0 960: d280000a mov x10, #0x0 // #0 mov x11, #0 964: d280000b mov x11, #0x0 // #0 mov x12, #0 968: d280000c mov x12, #0x0 // #0 mov x13, #0 96c: d280000d mov x13, #0x0 // #0 mov x14, #0 970: d280000e mov x14, #0x0 // #0 mov x15, #0 974: d280000f mov x15, #0x0 // #0 mov x16, #0 978: d2800010 mov x16, #0x0 // #0 mov x17, #0 97c: d2800011 mov x17, #0x0 // #0 mov x18, #0 980: d2800012 mov x18, #0x0 // #0 mov x19, #0 984: d2800013 mov x19, #0x0 // #0 mov x20, #0 988: d2800014 mov x20, #0x0 // #0 mov x21, #0 98c: d2800015 mov x21, #0x0 // #0 mov x22, #0 990: d2800016 mov x22, #0x0 // #0 mov x23, #0 994: d2800017 mov x23, #0x0 // #0 mov x24, #0 998: d2800018 mov x24, #0x0 // #0 mov x25, #0 99c: d2800019 mov x25, #0x0 // #0 mov x26, #0 9a0: d280001a mov x26, #0x0 // #0 mov x27, #0 9a4: d280001b mov x27, #0x0 // #0 mov x28, #0 9a8: d280001c mov x28, #0x0 // #0 mov x29, #0 9ac: d280001d mov x29, #0x0 // #0 mov x30, #0 9b0: d280001e mov x30, #0x0 // #0 00000000000009b4 : wfi b EndlessLoop0 #endif OKToRun: mrs x0, currentEL 9b4: d5384240 mrs x0, currentel cmp x0, #0xC 9b8: f100301f cmp x0, #0xc beq InitEL3 9bc: 54000080 b.eq 9cc // b.none cmp x0, #0x4 9c0: f100101f cmp x0, #0x4 beq InitEL1 9c4: 54000780 b.eq ab4 // b.none b error // go to error if current exception level is neither EL3 nor EL1 9c8: 1400003c b ab8 00000000000009cc : InitEL3: .if (EL3 == 1) /*Set vector table base address*/ ldr x1, =vector_base 9cc: 58000c21 ldr x1, b50 msr VBAR_EL3,x1 9d0: d51ec001 msr vbar_el3, x1 /* Set reset vector address */ /* Get the cpu ID */ mrs x0, MPIDR_EL1 9d4: d53800a0 mrs x0, mpidr_el1 and x0, x0, #0xFF 9d8: 92401c00 and x0, x0, #0xff mov w0, w0 9dc: 2a0003e0 mov w0, w0 ldr w2, =rvbar_base 9e0: 18000b42 ldr w2, b48 /* calculate the rvbar base address for particular CPU core */ mov w3, #0x8 9e4: 52800103 mov w3, #0x8 // #8 mul w0, w0, w3 9e8: 1b037c00 mul w0, w0, w3 add w2, w2, w0 9ec: 0b000042 add w2, w2, w0 /* store vector base address to RVBAR */ str x1, [x2] 9f0: f9000041 str x1, [x2] /*Define stack pointer for current exception level*/ ldr x2,=EL3_stack 9f4: 58000b22 ldr x2, b58 mov sp,x2 9f8: 9100005f mov sp, x2 /* Enable Trapping of SIMD/FPU register for standalone BSP */ mov x0, #0 9fc: d2800000 mov x0, #0x0 // #0 #ifndef FREERTOS_BSP orr x0, x0, #(0x1 << 10) a00: b2760000 orr x0, x0, #0x400 #endif msr CPTR_EL3, x0 a04: d51e1140 msr cptr_el3, x0 isb a08: d5033fdf isb * status of FPU i.e. disabled. In case of a warm restart execution * when bss sections are not cleared, it may contain previously updated * value which does not hold true now. */ #ifndef FREERTOS_BSP ldr x0,=FPUStatus a0c: 58000aa0 ldr x0, b60 str xzr, [x0] a10: f900001f str xzr, [x0] #endif /* Configure SCR_EL3 */ mov w1, #0 //; Initial value of register is unknown a14: 52800001 mov w1, #0x0 // #0 orr w1, w1, #(1 << 11) //; Set ST bit (Secure EL1 can access CNTPS_TVAL_EL1, CNTPS_CTL_EL1 & CNTPS_CVAL_EL1) a18: 32150021 orr w1, w1, #0x800 orr w1, w1, #(1 << 10) //; Set RW bit (EL1 is AArch64, as this is the Secure world) a1c: 32160021 orr w1, w1, #0x400 orr w1, w1, #(1 << 3) //; Set EA bit (SError routed to EL3) a20: 321d0021 orr w1, w1, #0x8 orr w1, w1, #(1 << 2) //; Set FIQ bit (FIQs routed to EL3) a24: 321e0021 orr w1, w1, #0x4 orr w1, w1, #(1 << 1) //; Set IRQ bit (IRQs routed to EL3) a28: 321f0021 orr w1, w1, #0x2 msr SCR_EL3, x1 a2c: d51e1101 msr scr_el3, x1 /*configure cpu auxiliary control register EL1 */ ldr x0,=0x80CA000 // L1 Data prefetch control - 5, Enable device split throttle, 2 independent data prefetch streams a30: 580009c0 ldr x0, b68 /* * Set ENDCCASCI bit in CPUACTLR_EL1 register, to execute data * cache clean operations as data cache clean and invalidate * */ orr x0, x0, #(1 << 44) //; Set ENDCCASCI bit a34: b2540000 orr x0, x0, #0x100000000000 #endif msr S3_1_C15_C2_0, x0 //CPUACTLR_EL1 a38: d519f200 msr s3_1_c15_c2_0, x0 /* program the counter frequency */ ldr x0,=counterfreq a3c: 580009a0 ldr x0, b70 msr CNTFRQ_EL0, x0 a40: d51be000 msr cntfrq_el0, x0 /*Enable hardware coherency between cores*/ mrs x0, S3_1_c15_c2_1 //Read EL1 CPU Extended Control Register a44: d539f220 mrs x0, s3_1_c15_c2_1 orr x0, x0, #(1 << 6) //Set the SMPEN bit a48: b27a0000 orr x0, x0, #0x40 msr S3_1_c15_c2_1, x0 //Write EL1 CPU Extended Control Register a4c: d519f220 msr s3_1_c15_c2_1, x0 isb a50: d5033fdf isb tlbi ALLE3 a54: d50e871f tlbi alle3 ic IALLU //; Invalidate I cache to PoU a58: d508751f ic iallu bl invalidate_dcaches a5c: 94000018 bl abc dsb sy a60: d5033f9f dsb sy isb a64: d5033fdf isb ldr x1, =L0Table //; Get address of level 0 for TTBR0_EL3 a68: 58000881 ldr x1, b78 msr TTBR0_EL3, x1 //; Set TTBR0_EL3 a6c: d51e2001 msr ttbr0_el3, x1 * 1 = b11111111 = Normal, Inner/Outer WB/WA/RA * 2 = b00000000 = Device-nGnRnE * 3 = b00000100 = Device-nGnRE * 4 = b10111011 = Normal, Inner/Outer WT/WA/RA **********************************************/ ldr x1, =0x000000BB0400FF44 a70: 58000881 ldr x1, b80 msr MAIR_EL3, x1 a74: d51ea201 msr mair_el3, x1 * Set up TCR_EL3 * Physical Address Size PS = 010 -> 40bits 1TB * Granual Size TG0 = 00 -> 4KB * size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40) ***************************************************/ ldr x1,=0x80823518 a78: 58000881 ldr x1, b88 msr TCR_EL3, x1 a7c: d51e2041 msr tcr_el3, x1 isb a80: d5033fdf isb /* Enable SError Exception for asynchronous abort */ mrs x1,DAIF a84: d53b4221 mrs x1, daif bic x1,x1,#(0x1<<8) a88: 9277f821 and x1, x1, #0xfffffffffffffeff msr DAIF,x1 a8c: d51b4221 msr daif, x1 /* Configure SCTLR_EL3 */ mov x1, #0 //Most of the SCTLR_EL3 bits are unknown at reset a90: d2800001 mov x1, #0x0 // #0 orr x1, x1, #(1 << 12) //Enable I cache a94: b2740021 orr x1, x1, #0x1000 orr x1, x1, #(1 << 3) //Enable SP alignment check a98: b27d0021 orr x1, x1, #0x8 orr x1, x1, #(1 << 2) //Enable caches a9c: b27e0021 orr x1, x1, #0x4 orr x1, x1, #(1 << 0) //Enable MMU aa0: b2400021 orr x1, x1, #0x1 msr SCTLR_EL3, x1 aa4: d51e1001 msr sctlr_el3, x1 dsb sy aa8: d5033f9f dsb sy isb aac: d5033fdf isb b _startup //jump to start ab0: 14000102 b eb8 <_startup> 0000000000000ab4 : ldr x1,=0x285800518 msr TCR_EL1, x1 isb /* Enable SError Exception for asynchronous abort */ mrs x1,DAIF bic x1,x1,#(0x1<<8) ab4: 14000001 b ab8 0000000000000ab8 : msr DAIF,x1 //; Enable MMU ab8: 14000000 b ab8 0000000000000abc : mov x1,#0x0 orr x1, x1, #(1 << 18) // ; Set WFE non trapping orr x1, x1, #(1 << 17) // ; Set WFI non trapping orr x1, x1, #(1 << 5) // ; Set CP15 barrier enabled orr x1, x1, #(1 << 12) // ; Set I bit abc: d5033bbf dmb ish orr x1, x1, #(1 << 2) // ; Set C bit ac0: d5390020 mrs x0, clidr_el1 orr x1, x1, #(1 << 0) // ; Set M bit ac4: 53186802 ubfx w2, w0, #24, #3 msr SCTLR_EL1, x1 ac8: 7100005f cmp w2, #0x0 isb acc: 540003c0 b.eq b44 // b.none ad0: 52800001 mov w1, #0x0 // #0 0000000000000ad4 : bl _startup //jump to start .else b error // present exception level and selected exception level mismatch ad4: 0b010423 add w3, w1, w1, lsl #1 .endif ad8: 1ac32403 lsr w3, w0, w3 adc: 53000863 ubfx w3, w3, #0, #3 error: b error ae0: 7100087f cmp w3, #0x2 ae4: 540002ab b.lt b38 // b.tstop invalidate_dcaches: ae8: 531f7824 lsl w4, w1, #1 aec: d51a0004 msr csselr_el1, x4 dmb ISH af0: d5033fdf isb mrs x0, CLIDR_EL1 //; x0 = CLIDR af4: d5390004 mrs x4, ccsidr_el1 ubfx w2, w0, #24, #3 //; w2 = CLIDR.LoC cmp w2, #0 //; LoC is 0? af8: 53000883 ubfx w3, w4, #0, #3 b.eq invalidateCaches_end //; No cleaning required and enable MMU afc: 11000863 add w3, w3, #0x2 mov w1, #0 //; w1 = level iterator b00: 530d6c85 ubfx w5, w4, #13, #15 b04: 53033084 ubfx w4, w4, #3, #10 invalidateCaches_flush_level: b08: 5ac01086 clz w6, w4 0000000000000b0c : add w3, w1, w1, lsl #1 //; w3 = w1 * 3 (right-shift for cache type) lsr w3, w0, w3 //; w3 = w0 >> w3 ubfx w3, w3, #0, #3 //; w3 = cache type of this level b0c: 2a0403e8 mov w8, w4 0000000000000b10 : cmp w3, #2 //; No cache at this level? b.lt invalidateCaches_next_level b10: 531f7827 lsl w7, w1, #1 b14: 1ac320a9 lsl w9, w5, w3 lsl w4, w1, #1 b18: 2a0900e7 orr w7, w7, w9 msr CSSELR_EL1, x4 //; Select current cache level in CSSELR b1c: 1ac62109 lsl w9, w8, w6 isb //; ISB required to reflect new CSIDR b20: 2a0900e7 orr w7, w7, w9 mrs x4, CCSIDR_EL1 //; w4 = CSIDR b24: d5087e47 dc cisw, x7 b28: 71000508 subs w8, w8, #0x1 ubfx w3, w4, #0, #3 b2c: 54ffff2a b.ge b10 // b.tcont add w3, w3, #2 //; w3 = log2(line size) b30: 710004a5 subs w5, w5, #0x1 ubfx w5, w4, #13, #15 b34: 54fffeca b.ge b0c // b.tcont 0000000000000b38 : ubfx w4, w4, #3, #10 //; w4 = Way number clz w6, w4 //; w6 = 32 - log2(number of ways) b38: 11000421 add w1, w1, #0x1 invalidateCaches_flush_set: b3c: 6b01005f cmp w2, w1 mov w8, w4 //; w8 = Way number b40: 54fffcac b.gt ad4 0000000000000b44 : invalidateCaches_flush_way: lsl w7, w1, #1 //; Fill level field lsl w9, w5, w3 b44: d65f03c0 ret b48: fd5c0040 .word 0xfd5c0040 ... b58: 0000e0c0 .word 0x0000e0c0 b5c: 00000000 .word 0x00000000 b60: 00000918 .word 0x00000918 b64: 00000000 .word 0x00000000 b68: 080ca000 .word 0x080ca000 b6c: 00000000 .word 0x00000000 b70: 05f5b9f5 .word 0x05f5b9f5 b74: 00000000 .word 0x00000000 b78: 00003000 .word 0x00003000 b7c: 00000000 .word 0x00000000 b80: 0400ff44 .word 0x0400ff44 b84: 000000bb .word 0x000000bb b88: 80823518 .word 0x80823518 b8c: 00000000 .word 0x00000000 0000000000000b90 : b90: d0000000 adrp x0, 2000 <_HEAP_SIZE> b94: 91008000 add x0, x0, #0x20 b98: d0000001 adrp x1, 2000 <_HEAP_SIZE> b9c: 91008021 add x1, x1, #0x20 ba0: eb00003f cmp x1, x0 ba4: 540000a0 b.eq bb8 // b.none ba8: b0000001 adrp x1, 1000 bac: f9436c21 ldr x1, [x1, #1752] bb0: b4000041 cbz x1, bb8 bb4: d61f0020 br x1 bb8: d65f03c0 ret bbc: d503201f nop 0000000000000bc0 : bc0: d0000000 adrp x0, 2000 <_HEAP_SIZE> bc4: 91008000 add x0, x0, #0x20 bc8: d0000001 adrp x1, 2000 <_HEAP_SIZE> bcc: 91008021 add x1, x1, #0x20 bd0: cb000021 sub x1, x1, x0 bd4: 9343fc21 asr x1, x1, #3 bd8: 8b41fc21 add x1, x1, x1, lsr #63 bdc: 9341fc21 asr x1, x1, #1 be0: b40000a1 cbz x1, bf4 be4: b0000002 adrp x2, 1000 be8: f9437042 ldr x2, [x2, #1760] bec: b4000042 cbz x2, bf4 bf0: d61f0040 br x2 bf4: d65f03c0 ret 0000000000000bf8 <__do_global_dtors_aux>: bf8: a9be7bfd stp x29, x30, [sp, #-32]! bfc: 910003fd mov x29, sp c00: f9000bf3 str x19, [sp, #16] c04: d0000053 adrp x19, a000 <__exidx_end> c08: 39420260 ldrb w0, [x19, #128] c0c: 35000140 cbnz w0, c34 <__do_global_dtors_aux+0x3c> c10: 97ffffe0 bl b90 c14: b0000000 adrp x0, 1000 c18: f9437400 ldr x0, [x0, #1768] c1c: b4000080 cbz x0, c2c <__do_global_dtors_aux+0x34> c20: d0000000 adrp x0, 2000 <_HEAP_SIZE> c24: 91010000 add x0, x0, #0x40 c28: d503201f nop c2c: 52800020 mov w0, #0x1 // #1 c30: 39020260 strb w0, [x19, #128] c34: f9400bf3 ldr x19, [sp, #16] c38: a8c27bfd ldp x29, x30, [sp], #32 c3c: d65f03c0 ret 0000000000000c40 : c40: b0000000 adrp x0, 1000 c44: f9437800 ldr x0, [x0, #1776] c48: b4000140 cbz x0, c70 c4c: a9bf7bfd stp x29, x30, [sp, #-16]! c50: d0000041 adrp x1, a000 <__exidx_end> c54: d0000000 adrp x0, 2000 <_HEAP_SIZE> c58: 91022021 add x1, x1, #0x88 c5c: 910003fd mov x29, sp c60: 91010000 add x0, x0, #0x40 c64: d503201f nop c68: a8c17bfd ldp x29, x30, [sp], #16 c6c: 17ffffd5 b bc0 c70: 17ffffd4 b bc0 c74: 00000000 .inst 0x00000000 ; undefined 0000000000000c78 <_mainCRTStartup>: c78: 100007c1 adr x1, d70 <_cpu_init_hook+0x4> c7c: 528002c0 mov w0, #0x16 // #22 c80: d45e0000 hlt #0xf000 c84: 58000760 ldr x0, d70 <_cpu_init_hook+0x4> c88: f9400401 ldr x1, [x0, #8] c8c: 927cec20 and x0, x1, #0xfffffffffffffff0 c90: 9100001f mov sp, x0 c94: d280001d mov x29, #0x0 // #0 c98: a9bf77fd stp x29, x29, [sp, #-16]! c9c: 910003fd mov x29, sp ca0: 94000033 bl d6c <_cpu_init_hook> ca4: 580006a0 ldr x0, d78 <_cpu_init_hook+0xc> ca8: 52800001 mov w1, #0x0 // #0 cac: 580006a2 ldr x2, d80 <_cpu_init_hook+0x14> cb0: cb000042 sub x2, x2, x0 cb4: 94000143 bl 11c0 cb8: 9400005a bl e20 cbc: 58000660 ldr x0, d88 <_cpu_init_hook+0x1c> cc0: 940000f0 bl 1080 cc4: 94000115 bl 1118 <__libc_init_array> cc8: 10000681 adr x1, d98 <_cpu_init_hook+0x2c> ccc: 528002a0 mov w0, #0x15 // #21 cd0: d45e0000 hlt #0xf000 cd4: 58000628 ldr x8, d98 <_cpu_init_hook+0x2c> cd8: d2800000 mov x0, #0x0 // #0 cdc: 910003e1 mov x1, sp ce0: 58000582 ldr x2, d90 <_cpu_init_hook+0x24> ce4: f81f8c20 str x0, [x1, #-8]! ce8: 38401503 ldrb w3, [x8], #1 cec: 34000243 cbz w3, d34 <_mainCRTStartup+0xbc> cf0: 7100807f cmp w3, #0x20 cf4: 54ffffa0 b.eq ce8 <_mainCRTStartup+0x70> // b.none cf8: 52800404 mov w4, #0x20 // #32 cfc: 71008869 subs w9, w3, #0x22 d00: d1000508 sub x8, x8, #0x1 d04: 7a451924 ccmp w9, #0x5, #0x4, ne // ne = any d08: 1a840064 csel w4, w3, w4, eq // eq = none d0c: 9a881508 cinc x8, x8, eq // eq = none d10: f81f8c28 str x8, [x1, #-8]! d14: 91000400 add x0, x0, #0x1 d18: 38401503 ldrb w3, [x8], #1 d1c: 340000c3 cbz w3, d34 <_mainCRTStartup+0xbc> d20: 6b03009f cmp w4, w3 d24: 54ffffa1 b.ne d18 <_mainCRTStartup+0xa0> // b.any d28: 52800004 mov w4, #0x0 // #0 d2c: 381ff104 sturb w4, [x8, #-1] d30: 17ffffee b ce8 <_mainCRTStartup+0x70> d34: 91000023 add x3, x1, #0x0 d38: 8b204c24 add x4, x1, w0, uxtw #3 d3c: eb03009f cmp x4, x3 d40: 540000e3 b.cc d5c <_mainCRTStartup+0xe4> // b.lo, b.ul, b.last d44: f85f8085 ldur x5, [x4, #-8] d48: f9400066 ldr x6, [x3] d4c: f81f8c86 str x6, [x4, #-8]! d50: f8008465 str x5, [x3], #8 d54: eb03009f cmp x4, x3 d58: 54ffff68 b.hi d44 <_mainCRTStartup+0xcc> // b.pmore d5c: 927cec24 and x4, x1, #0xfffffffffffffff0 d60: 9100009f mov sp, x4 d64: 94000011 bl da8
d68: 140000cc b 1098 0000000000000d6c <_cpu_init_hook>: d6c: d65f03c0 ret d70: 00001748 .word 0x00001748 d74: 00000000 .word 0x00000000 d78: 0000a080 .word 0x0000a080 d7c: 00000000 .word 0x00000000 d80: 0000a0c0 .word 0x0000a0c0 d84: 00000000 .word 0x00000000 d88: 000010d0 .word 0x000010d0 d8c: 00000000 .word 0x00000000 d90: 00001768 .word 0x00001768 d94: 00000000 .word 0x00000000 d98: 00001770 .word 0x00001770 d9c: 00000000 .word 0x00000000 da0: 000000ff .word 0x000000ff da4: 00000000 .word 0x00000000 0000000000000da8
: #include "platform.h" #include "xil_printf.h" int main() { da8: a9bf7bfd stp x29, x30, [sp, #-16]! dac: 910003fd mov x29, sp init_platform(); db0: 9400000e bl de8 print("Hello World\n\r"); db4: b0000000 adrp x0, 1000 db8: 911b0000 add x0, x0, #0x6c0 dbc: 9400001b bl e28 cleanup_platform(); dc0: 94000011 bl e04 return 0; dc4: 52800000 mov w0, #0x0 // #0 } dc8: a8c17bfd ldp x29, x30, [sp], #16 dcc: d65f03c0 ret 0000000000000dd0 : #endif #ifdef XPAR_MICROBLAZE_USE_DCACHE Xil_DCacheEnable(); #endif #endif } dd0: d503201f nop dd4: d65f03c0 ret 0000000000000dd8 : #endif #ifdef XPAR_MICROBLAZE_USE_ICACHE Xil_ICacheDisable(); #endif #endif } dd8: d503201f nop ddc: d65f03c0 ret 0000000000000de0 : #ifdef STDOUT_IS_16550 XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD); XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS); #endif /* Bootrom/BSP configures PS7/PSU UART to 115200 bps */ } de0: d503201f nop de4: d65f03c0 ret 0000000000000de8 : void init_platform() { de8: a9bf7bfd stp x29, x30, [sp, #-16]! dec: 910003fd mov x29, sp * Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included * along with this example source files for compilation. */ /* ps7_init();*/ /* psu_init();*/ enable_caches(); df0: 97fffff8 bl dd0 init_uart(); df4: 97fffffb bl de0 } df8: d503201f nop dfc: a8c17bfd ldp x29, x30, [sp], #16 e00: d65f03c0 ret 0000000000000e04 : void cleanup_platform() { e04: a9bf7bfd stp x29, x30, [sp, #-16]! e08: 910003fd mov x29, sp disable_caches(); e0c: 97fffff3 bl dd8 } e10: d503201f nop e14: a8c17bfd ldp x29, x30, [sp], #16 e18: d65f03c0 ret e1c: 00000000 .inst 0x00000000 ; undefined 0000000000000e20 : * 5.00 pkp 05/29/14 First release * ******************************************************************************/ __attribute__((weak)) void initialise_monitor_handles(){ } e20: d65f03c0 ret e24: 00000000 .inst 0x00000000 ; undefined 0000000000000e28 : * print -- do a raw print of a string */ #include "xil_printf.h" void print(const char8 *ptr) { e28: a9be7bfd stp x29, x30, [sp, #-32]! e2c: 910003fd mov x29, sp e30: f9000bf3 str x19, [sp, #16] e34: aa0003f3 mov x19, x0 #if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE XPVXenConsole_Write(ptr); #else #ifdef STDOUT_BASEADDRESS while (*ptr != (char8)0) { e38: 39400000 ldrb w0, [x0] e3c: 34000080 cbz w0, e4c outbyte (*ptr); e40: 94000060 bl fc0 while (*ptr != (char8)0) { e44: 38401e60 ldrb w0, [x19, #1]! e48: 35ffffc0 cbnz w0, e40 } #else (void)ptr; #endif #endif } e4c: f9400bf3 ldr x19, [sp, #16] e50: a8c27bfd ldp x29, x30, [sp], #32 e54: d65f03c0 ret 0000000000000e58 : * @note None. * ******************************************************************************/ void FIQInterrupt(void) { XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[ e58: b0000000 adrp x0, 1000 e5c: 9121c000 add x0, x0, #0x870 e60: a9430001 ldp x1, x0, [x0, #48] e64: d61f0020 br x1 0000000000000e68 : * @note None. * ******************************************************************************/ void IRQInterrupt(void) { XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[ e68: b0000000 adrp x0, 1000 e6c: 9121c000 add x0, x0, #0x870 e70: a9420001 ldp x1, x0, [x0, #32] e74: d61f0020 br x1 0000000000000e78 : * @note None. * ******************************************************************************/ void SynchronousInterrupt(void) { XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[ e78: b0000000 adrp x0, 1000 e7c: 9121c000 add x0, x0, #0x870 e80: a9410001 ldp x1, x0, [x0, #16] e84: d61f0020 br x1 0000000000000e88 : * @note None. * ******************************************************************************/ void SErrorInterrupt(void) { XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler( e88: b0000000 adrp x0, 1000 e8c: 9121c000 add x0, x0, #0x870 e90: a9440001 ldp x1, x0, [x0, #64] e94: d61f0020 br x1 e98: 0000a080 .word 0x0000a080 e9c: 00000000 .word 0x00000000 ea0: 0000a080 .word 0x0000a080 ea4: 00000000 .word 0x00000000 ea8: 0000a080 .word 0x0000a080 eac: 00000000 .word 0x00000000 eb0: 0000a0c0 .word 0x0000a0c0 eb4: 00000000 .word 0x00000000 0000000000000eb8 <_startup>: .set APU_PWRCTL, 0xFD5C0090 .globl _startup _startup: mov x0, #0 eb8: d2800000 mov x0, #0x0 // #0 .if (EL3 == 1) /* Check whether the clearing of bss sections shall be skipped */ ldr x10, =APU_PWRCTL /* Load PWRCTRL address */ ebc: 5800036a ldr x10, f28 <_startup+0x70> ldr w11, [x10] /* Read PWRCTRL register */ ec0: b940014b ldr w11, [x10] mrs x2, MPIDR_EL1 /* Read MPIDR_EL1 */ ec4: d53800a2 mrs x2, mpidr_el1 ubfx x2, x2, #0, #8 /* Extract CPU ID (affinity level 0) */ ec8: d3401c42 ubfx x2, x2, #0, #8 mov w1, #1 ecc: 52800021 mov w1, #0x1 // #1 lsl w2, w1, w2 /* Shift CPU ID to get one-hot ID */ ed0: 1ac22022 lsl w2, w1, w2 ands w11, w11, w2 /* Get PWRCTRL bit for this core */ ed4: 6a02016b ands w11, w11, w2 bne .Lenclbss /* Skip BSS and SBSS clearing */ ed8: 540001a1 b.ne f0c <_startup+0x54> // b.any .endif /* clear sbss */ ldr x1,.Lsbss_start /* calculate beginning of the SBSS */ edc: 58fffde1 ldr x1, e98 ldr x2,.Lsbss_end /* calculate end of the SBSS */ ee0: 58fffe02 ldr x2, ea0 .Lloop_sbss: cmp x1,x2 ee4: eb02003f cmp x1, x2 bge .Lenclsbss /* If no SBSS, no clearing required */ ee8: 5400006a b.ge ef4 <_startup+0x3c> // b.tcont str x0, [x1], #8 eec: f8008420 str x0, [x1], #8 b .Lloop_sbss ef0: 17fffffd b ee4 <_startup+0x2c> .Lenclsbss: /* clear bss */ ldr x1,.Lbss_start /* calculate beginning of the BSS */ ef4: 58fffda1 ldr x1, ea8 ldr x2,.Lbss_end /* calculate end of the BSS */ ef8: 58fffdc2 ldr x2, eb0 .Lloop_bss: cmp x1,x2 efc: eb02003f cmp x1, x2 bge .Lenclbss /* If no BSS, no clearing required */ f00: 5400006a b.ge f0c <_startup+0x54> // b.tcont str x0, [x1], #8 f04: f8008420 str x0, [x1], #8 b .Lloop_bss f08: 17fffffd b efc <_startup+0x44> .Lenclbss: /* run global constructors */ bl __libc_init_array f0c: 94000083 bl 1118 <__libc_init_array> .if (EL1_NONSECURE == 1 && HYP_GUEST == 1 && \ XEN_USE_PV_CONSOLE == 1) bl XPVXenConsole_Init .endif /* make sure argc and argv are valid */ mov x0, #0 f10: d2800000 mov x0, #0x0 // #0 mov x1, #0 f14: d2800001 mov x1, #0x0 // #0 bl main /* Jump to main C code */ f18: 97ffffa4 bl da8
/* Cleanup global constructors */ bl __libc_fini_array f1c: 9400006d bl 10d0 <__libc_fini_array> bl exit f20: 9400005e bl 1098 .Lexit: /* should never get here */ b .Lexit f24: 14000000 b f24 <_startup+0x6c> f28: fd5c0090 .word 0xfd5c0090 f2c: 00000000 .word 0x00000000 0000000000000f30 : * * @note None. * *****************************************************************************/ static void Xil_ExceptionNullHandler(void *Data) { f30: 14000000 b f30 f34: d503201f nop 0000000000000f38 : * * @note None. * ****************************************************************************/ void Xil_SyncAbortHandler(void *CallBackRef){ f38: 14000000 b f38 f3c: d503201f nop 0000000000000f40 : * @return None. * * @note None. * ****************************************************************************/ void Xil_SErrorAbortHandler(void *CallBackRef){ f40: 14000000 b f40 f44: d503201f nop 0000000000000f48 : } f48: d65f03c0 ret f4c: d503201f nop 0000000000000f50 : XExc_VectorTable[Exception_id].Handler = Handler; f50: d37c7c00 ubfiz x0, x0, #4, #32 f54: b0000003 adrp x3, 1000 f58: 9121c063 add x3, x3, #0x870 f5c: 8b000064 add x4, x3, x0 f60: f8206861 str x1, [x3, x0] XExc_VectorTable[Exception_id].Data = Data; f64: f9000482 str x2, [x4, #8] } f68: d65f03c0 ret f6c: d503201f nop 0000000000000f70 : *Handler = XExc_VectorTable[Exception_id].Handler; f70: d37c7c00 ubfiz x0, x0, #4, #32 f74: b0000003 adrp x3, 1000 f78: 9121c063 add x3, x3, #0x870 f7c: 8b000064 add x4, x3, x0 f80: f8606860 ldr x0, [x3, x0] f84: f9000020 str x0, [x1] *Data = XExc_VectorTable[Exception_id].Data; f88: f9400480 ldr x0, [x4, #8] f8c: f9000040 str x0, [x2] } f90: d65f03c0 ret f94: d503201f nop 0000000000000f98 : XExc_VectorTable[Exception_id].Handler = Handler; f98: d37c7c00 ubfiz x0, x0, #4, #32 f9c: b0000001 adrp x1, 1000 fa0: 9121c021 add x1, x1, #0x870 fa4: 90000002 adrp x2, 0 <_vector_table> fa8: 8b000023 add x3, x1, x0 fac: 913cc042 add x2, x2, #0xf30 fb0: f8206822 str x2, [x1, x0] XExc_VectorTable[Exception_id].Data = Data; fb4: f900047f str xzr, [x3, #8] } fb8: d65f03c0 ret fbc: 00000000 .inst 0x00000000 ; undefined 0000000000000fc0 : #ifdef __cplusplus } #endif void outbyte(char c) { XUartPs_SendByte(STDOUT_BASEADDRESS, c); fc0: 2a0003e1 mov w1, w0 fc4: 52bfe000 mov w0, #0xff000000 // #-16777216 fc8: 14000002 b fd0 fcc: 00000000 .inst 0x00000000 ; undefined 0000000000000fd0 : * * @note None. * *****************************************************************************/ void XUartPs_SendByte(u32 BaseAddress, u8 Data) { fd0: 12001c21 and w1, w1, #0xff fd4: 1100b003 add w3, w0, #0x2c * @return The 32 bit Value read from the specified input address. * ******************************************************************************/ static INLINE u32 Xil_In32(UINTPTR Addr) { return *(volatile u32 *) Addr; fd8: b9400062 ldr w2, [x3] /* Wait until there is space in TX FIFO */ while (XUartPs_IsTransmitFull(BaseAddress)) { fdc: 3727ffe2 tbnz w2, #4, fd8 ; } /* Write the byte into the TX FIFO */ XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data); fe0: 1100c000 add w0, w0, #0x30 ******************************************************************************/ static INLINE void Xil_Out32(UINTPTR Addr, u32 Value) { #ifndef ENABLE_SAFETY volatile u32 *LocalAddr = (volatile u32 *)Addr; *LocalAddr = Value; fe4: b9000001 str w1, [x0] } fe8: d65f03c0 ret fec: d503201f nop 0000000000000ff0 : * * @note None. * *****************************************************************************/ u8 XUartPs_RecvByte(u32 BaseAddress) { ff0: 1100b002 add w2, w0, #0x2c ff4: d503201f nop return *(volatile u32 *) Addr; ff8: b9400041 ldr w1, [x2] u32 RecievedByte; /* Wait until there is data */ while (!XUartPs_IsReceiveData(BaseAddress)) { ffc: 370fffe1 tbnz w1, #1, ff8 ; } RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET); 1000: 1100c000 add w0, w0, #0x30 1004: b9400000 ldr w0, [x0] /* Return the byte received */ return (u8)RecievedByte; } 1008: d65f03c0 ret 100c: d503201f nop 0000000000001010 : *****************************************************************************/ void XUartPs_ResetHw(u32 BaseAddress) { /* Disable interrupts */ XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK); 1010: 11003006 add w6, w0, #0xc /* Disable receive and transmit */ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET, 1014: 2a0003e1 mov w1, w0 *LocalAddr = Value; 1018: 5287ffe2 mov w2, #0x3fff // #16383 */ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET, ((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST)); /* Clear status flags - SW reset wont clear sticky flags. */ XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK); 101c: 11005007 add w7, w0, #0x14 /* * Mode register reset value : All zeroes * Normal mode, even parity, 1 stop bit */ XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET, 1020: 11001004 add w4, w0, #0x4 1024: 52800505 mov w5, #0x28 // #40 1028: b90000c2 str w2, [x6] 102c: 52800063 mov w3, #0x3 // #3 1030: b9000025 str w5, [x1] XUARTPS_MR_CHMODE_NORM); /* Rx and TX trigger register reset values */ XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET, 1034: 11008006 add w6, w0, #0x20 1038: b9000023 str w3, [x1] XUARTPS_RXWM_RESET_VAL); XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET, 103c: 11011005 add w5, w0, #0x44 1040: b90000e2 str w2, [x7] XUARTPS_TXWM_RESET_VAL); /* Rx timeout disabled by default */ XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET, 1044: 11007003 add w3, w0, #0x1c 1048: b900009f str wzr, [x4] 104c: 52800402 mov w2, #0x20 // #32 XUARTPS_RXTOUT_DISABLE); /* Baud rate generator and dividor reset values */ XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET, 1050: 11006004 add w4, w0, #0x18 1054: b90000c2 str w2, [x6] 1058: b90000a2 str w2, [x5] XUARTPS_BAUDGEN_RESET_VAL); XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET, 105c: 1100d000 add w0, w0, #0x34 1060: b900007f str wzr, [x3] 1064: 52805162 mov w2, #0x28b // #651 1068: b9000082 str w2, [x4] 106c: 528001e3 mov w3, #0xf // #15 1070: b9000003 str w3, [x0] 1074: 52802502 mov w2, #0x128 // #296 1078: b9000022 str w2, [x1] */ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET, ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS | (u32)XUARTPS_CR_STOPBRK)); } 107c: d65f03c0 ret 0000000000001080 : 1080: aa0003e1 mov x1, x0 1084: d2800003 mov x3, #0x0 // #0 1088: d2800002 mov x2, #0x0 // #0 108c: 52800000 mov w0, #0x0 // #0 1090: 140000c2 b 1398 <__register_exitproc> 1094: 00000000 .inst 0x00000000 ; undefined 0000000000001098 : 1098: a9be7bfd stp x29, x30, [sp, #-32]! 109c: d2800001 mov x1, #0x0 // #0 10a0: 910003fd mov x29, sp 10a4: f9000bf3 str x19, [sp, #16] 10a8: 2a0003f3 mov w19, w0 10ac: 940000f9 bl 1490 <__call_exitprocs> 10b0: 90000000 adrp x0, 1000 10b4: f9436800 ldr x0, [x0, #1744] 10b8: f9402c01 ldr x1, [x0, #88] 10bc: b4000041 cbz x1, 10c4 10c0: d63f0020 blr x1 10c4: 2a1303e0 mov w0, w19 10c8: 94000148 bl 15e8 <_exit> 10cc: 00000000 .inst 0x00000000 ; undefined 00000000000010d0 <__libc_fini_array>: 10d0: a9be7bfd stp x29, x30, [sp, #-32]! 10d4: 90000001 adrp x1, 1000 10d8: 90000000 adrp x0, 1000 10dc: 910003fd mov x29, sp 10e0: a90153f3 stp x19, x20, [sp, #16] 10e4: f9437c33 ldr x19, [x1, #1784] 10e8: f9438014 ldr x20, [x0, #1792] 10ec: cb140273 sub x19, x19, x20 10f0: 9343fe73 asr x19, x19, #3 10f4: b40000b3 cbz x19, 1108 <__libc_fini_array+0x38> 10f8: d1000673 sub x19, x19, #0x1 10fc: f8737a80 ldr x0, [x20, x19, lsl #3] 1100: d63f0000 blr x0 1104: b5ffffb3 cbnz x19, 10f8 <__libc_fini_array+0x28> 1108: a94153f3 ldp x19, x20, [sp, #16] 110c: a8c27bfd ldp x29, x30, [sp], #32 1110: 1400014c b 1640 <_fini> 1114: 00000000 .inst 0x00000000 ; undefined 0000000000001118 <__libc_init_array>: 1118: a9bd7bfd stp x29, x30, [sp, #-48]! 111c: 90000001 adrp x1, 1000 1120: 90000000 adrp x0, 1000 1124: 910003fd mov x29, sp 1128: a90153f3 stp x19, x20, [sp, #16] 112c: f90013f5 str x21, [sp, #32] 1130: f9438834 ldr x20, [x1, #1808] 1134: f9438c15 ldr x21, [x0, #1816] 1138: cb150294 sub x20, x20, x21 113c: 9343fe94 asr x20, x20, #3 1140: b40000f4 cbz x20, 115c <__libc_init_array+0x44> 1144: d2800013 mov x19, #0x0 // #0 1148: f8737aa0 ldr x0, [x21, x19, lsl #3] 114c: 91000673 add x19, x19, #0x1 1150: d63f0000 blr x0 1154: eb13029f cmp x20, x19 1158: 54ffff81 b.ne 1148 <__libc_init_array+0x30> // b.any 115c: 94000129 bl 1600 <_init> 1160: 90000001 adrp x1, 1000 1164: 90000000 adrp x0, 1000 1168: f9439034 ldr x20, [x1, #1824] 116c: f9439415 ldr x21, [x0, #1832] 1170: cb150294 sub x20, x20, x21 1174: 9343fe94 asr x20, x20, #3 1178: b40000f4 cbz x20, 1194 <__libc_init_array+0x7c> 117c: d2800013 mov x19, #0x0 // #0 1180: f8737aa0 ldr x0, [x21, x19, lsl #3] 1184: 91000673 add x19, x19, #0x1 1188: d63f0000 blr x0 118c: eb13029f cmp x20, x19 1190: 54ffff81 b.ne 1180 <__libc_init_array+0x68> // b.any 1194: a94153f3 ldp x19, x20, [sp, #16] 1198: f94013f5 ldr x21, [sp, #32] 119c: a8c37bfd ldp x29, x30, [sp], #48 11a0: d65f03c0 ret ... 00000000000011c0 : 11c0: 4e010c20 dup v0.16b, w1 11c4: 8b020004 add x4, x0, x2 11c8: f101805f cmp x2, #0x60 11cc: 540003c8 b.hi 1244 // b.pmore 11d0: f100405f cmp x2, #0x10 11d4: 54000202 b.cs 1214 // b.hs, b.nlast 11d8: 4e083c01 mov x1, v0.d[0] 11dc: 361800a2 tbz w2, #3, 11f0 11e0: f9000001 str x1, [x0] 11e4: f81f8081 stur x1, [x4, #-8] 11e8: d65f03c0 ret 11ec: d503201f nop 11f0: 36100082 tbz w2, #2, 1200 11f4: b9000001 str w1, [x0] 11f8: b81fc081 stur w1, [x4, #-4] 11fc: d65f03c0 ret 1200: b4000082 cbz x2, 1210 1204: 39000001 strb w1, [x0] 1208: 36080042 tbz w2, #1, 1210 120c: 781fe081 sturh w1, [x4, #-2] 1210: d65f03c0 ret 1214: 3d800000 str q0, [x0] 1218: 373000c2 tbnz w2, #6, 1230 121c: 3c9f0080 stur q0, [x4, #-16] 1220: 36280062 tbz w2, #5, 122c 1224: 3d800400 str q0, [x0, #16] 1228: 3c9e0080 stur q0, [x4, #-32] 122c: d65f03c0 ret 1230: 3d800400 str q0, [x0, #16] 1234: ad010000 stp q0, q0, [x0, #32] 1238: ad3f0080 stp q0, q0, [x4, #-32] 123c: d65f03c0 ret 1240: d503201f nop 1244: 12001c21 and w1, w1, #0xff 1248: 927cec03 and x3, x0, #0xfffffffffffffff0 124c: 3d800000 str q0, [x0] 1250: f104005f cmp x2, #0x100 1254: 7a402820 ccmp w1, #0x0, #0x0, cs // cs = hs, nlast 1258: 54000180 b.eq 1288 // b.none 125c: cb030082 sub x2, x4, x3 1260: 91004063 add x3, x3, #0x10 1264: d1014042 sub x2, x2, #0x50 1268: ac820060 stp q0, q0, [x3], #64 126c: ad3f0060 stp q0, q0, [x3, #-32] 1270: f1010042 subs x2, x2, #0x40 1274: 54ffffa8 b.hi 1268 // b.pmore 1278: ad3e0080 stp q0, q0, [x4, #-64] 127c: ad3f0080 stp q0, q0, [x4, #-32] 1280: d65f03c0 ret 1284: d503201f nop 1288: d53b00e5 mrs x5, dczid_el0 128c: 3727fe85 tbnz w5, #4, 125c 1290: 12000ca5 and w5, w5, #0xf 1294: 710010bf cmp w5, #0x4 1298: 54000281 b.ne 12e8 // b.any 129c: 3d800460 str q0, [x3, #16] 12a0: ad010060 stp q0, q0, [x3, #32] 12a4: 927ae463 and x3, x3, #0xffffffffffffffc0 12a8: ad020060 stp q0, q0, [x3, #64] 12ac: ad030060 stp q0, q0, [x3, #96] 12b0: cb030082 sub x2, x4, x3 12b4: d1040042 sub x2, x2, #0x100 12b8: 91020063 add x3, x3, #0x80 12bc: d503201f nop 12c0: d50b7423 dc zva, x3 12c4: 91010063 add x3, x3, #0x40 12c8: f1010042 subs x2, x2, #0x40 12cc: 54ffffa8 b.hi 12c0 // b.pmore 12d0: ad000060 stp q0, q0, [x3] 12d4: ad010060 stp q0, q0, [x3, #32] 12d8: ad3e0080 stp q0, q0, [x4, #-64] 12dc: ad3f0080 stp q0, q0, [x4, #-32] 12e0: d65f03c0 ret 12e4: d503201f nop 12e8: 710014bf cmp w5, #0x5 12ec: 54000241 b.ne 1334 // b.any 12f0: 3d800460 str q0, [x3, #16] 12f4: ad010060 stp q0, q0, [x3, #32] 12f8: ad020060 stp q0, q0, [x3, #64] 12fc: ad030060 stp q0, q0, [x3, #96] 1300: 9279e063 and x3, x3, #0xffffffffffffff80 1304: cb030082 sub x2, x4, x3 1308: d1040042 sub x2, x2, #0x100 130c: 91020063 add x3, x3, #0x80 1310: d50b7423 dc zva, x3 1314: 91020063 add x3, x3, #0x80 1318: f1020042 subs x2, x2, #0x80 131c: 54ffffa8 b.hi 1310 // b.pmore 1320: ad3c0080 stp q0, q0, [x4, #-128] 1324: ad3d0080 stp q0, q0, [x4, #-96] 1328: ad3e0080 stp q0, q0, [x4, #-64] 132c: ad3f0080 stp q0, q0, [x4, #-32] 1330: d65f03c0 ret 1334: 52800086 mov w6, #0x4 // #4 1338: 1ac520c7 lsl w7, w6, w5 133c: 910100e5 add x5, x7, #0x40 1340: eb05005f cmp x2, x5 1344: 54fff8c3 b.cc 125c // b.lo, b.ul, b.last 1348: d10004e6 sub x6, x7, #0x1 134c: 8b070065 add x5, x3, x7 1350: 91004063 add x3, x3, #0x10 1354: eb0300a2 subs x2, x5, x3 1358: 8a2600a5 bic x5, x5, x6 135c: 540000a0 b.eq 1370 // b.none 1360: ac820060 stp q0, q0, [x3], #64 1364: ad3f0060 stp q0, q0, [x3, #-32] 1368: f1010042 subs x2, x2, #0x40 136c: 54ffffa8 b.hi 1360 // b.pmore 1370: aa0503e3 mov x3, x5 1374: cb050082 sub x2, x4, x5 1378: eb070042 subs x2, x2, x7 137c: 540000a3 b.cc 1390 // b.lo, b.ul, b.last 1380: d50b7423 dc zva, x3 1384: 8b070063 add x3, x3, x7 1388: eb070042 subs x2, x2, x7 138c: 54ffffa2 b.cs 1380 // b.hs, b.nlast 1390: 8b070042 add x2, x2, x7 1394: 17ffffb7 b 1270 0000000000001398 <__register_exitproc>: 1398: a9bc7bfd stp x29, x30, [sp, #-64]! 139c: 90000004 adrp x4, 1000 13a0: 910003fd mov x29, sp 13a4: a90153f3 stp x19, x20, [sp, #16] 13a8: 2a0003f4 mov w20, w0 13ac: f9436893 ldr x19, [x4, #1744] 13b0: a9025bf5 stp x21, x22, [sp, #32] 13b4: aa0103f5 mov x21, x1 13b8: aa0303f6 mov x22, x3 13bc: f940fe64 ldr x4, [x19, #504] 13c0: f9001bf7 str x23, [sp, #48] 13c4: aa0203f7 mov x23, x2 13c8: b4000584 cbz x4, 1478 <__register_exitproc+0xe0> 13cc: b9400880 ldr w0, [x4, #8] 13d0: 11000401 add w1, w0, #0x1 13d4: 71007c1f cmp w0, #0x1f 13d8: 540001ed b.le 1414 <__register_exitproc+0x7c> 13dc: 90000000 adrp x0, 1000 13e0: f9439800 ldr x0, [x0, #1840] 13e4: b4000500 cbz x0, 1484 <__register_exitproc+0xec> 13e8: d2806300 mov x0, #0x318 // #792 13ec: d503201f nop 13f0: aa0003e4 mov x4, x0 13f4: b4000480 cbz x0, 1484 <__register_exitproc+0xec> 13f8: f940fe60 ldr x0, [x19, #504] 13fc: 52800021 mov w1, #0x1 // #1 1400: f9000080 str x0, [x4] 1404: b900089f str wzr, [x4, #8] 1408: 52800000 mov w0, #0x0 // #0 140c: f900fe64 str x4, [x19, #504] 1410: f901889f str xzr, [x4, #784] 1414: 93407c05 sxtw x5, w0 1418: 35000154 cbnz w20, 1440 <__register_exitproc+0xa8> 141c: 910008a5 add x5, x5, #0x2 1420: b9000881 str w1, [x4, #8] 1424: 52800000 mov w0, #0x0 // #0 1428: f8257895 str x21, [x4, x5, lsl #3] 142c: a94153f3 ldp x19, x20, [sp, #16] 1430: a9425bf5 ldp x21, x22, [sp, #32] 1434: f9401bf7 ldr x23, [sp, #48] 1438: a8c47bfd ldp x29, x30, [sp], #64 143c: d65f03c0 ret 1440: 8b050c83 add x3, x4, x5, lsl #3 1444: 52800026 mov w6, #0x1 // #1 1448: 1ac020c0 lsl w0, w6, w0 144c: 71000a9f cmp w20, #0x2 1450: f9008877 str x23, [x3, #272] 1454: b9431082 ldr w2, [x4, #784] 1458: 2a000042 orr w2, w2, w0 145c: b9031082 str w2, [x4, #784] 1460: f9010876 str x22, [x3, #528] 1464: 54fffdc1 b.ne 141c <__register_exitproc+0x84> // b.any 1468: b9431482 ldr w2, [x4, #788] 146c: 2a000040 orr w0, w2, w0 1470: b9031480 str w0, [x4, #788] 1474: 17ffffea b 141c <__register_exitproc+0x84> 1478: 91080264 add x4, x19, #0x200 147c: f900fe64 str x4, [x19, #504] 1480: 17ffffd3 b 13cc <__register_exitproc+0x34> 1484: 12800000 mov w0, #0xffffffff // #-1 1488: 17ffffe9 b 142c <__register_exitproc+0x94> 148c: 00000000 .inst 0x00000000 ; undefined 0000000000001490 <__call_exitprocs>: 1490: a9b97bfd stp x29, x30, [sp, #-112]! 1494: 90000002 adrp x2, 1000 1498: 910003fd mov x29, sp 149c: a90363f7 stp x23, x24, [sp, #48] 14a0: f9436857 ldr x23, [x2, #1744] 14a4: a90573fb stp x27, x28, [sp, #80] 14a8: aa0103fb mov x27, x1 14ac: 9107e2f8 add x24, x23, #0x1f8 14b0: a90153f3 stp x19, x20, [sp, #16] 14b4: a9025bf5 stp x21, x22, [sp, #32] 14b8: 52800036 mov w22, #0x1 // #1 14bc: a9046bf9 stp x25, x26, [sp, #64] 14c0: 90000019 adrp x25, 1000 14c4: b9006fa0 str w0, [x29, #108] 14c8: f940fef5 ldr x21, [x23, #504] 14cc: b4000355 cbz x21, 1534 <__call_exitprocs+0xa4> 14d0: aa1803fa mov x26, x24 14d4: b9400ab3 ldr w19, [x21, #8] 14d8: 71000673 subs w19, w19, #0x1 14dc: 54000164 b.mi 1508 <__call_exitprocs+0x78> // b.first 14e0: 8b33ceb4 add x20, x21, w19, sxtw #3 14e4: d503201f nop 14e8: b400035b cbz x27, 1550 <__call_exitprocs+0xc0> 14ec: f9410a80 ldr x0, [x20, #528] 14f0: eb1b001f cmp x0, x27 14f4: 540002e0 b.eq 1550 <__call_exitprocs+0xc0> // b.none 14f8: 51000673 sub w19, w19, #0x1 14fc: d1002294 sub x20, x20, #0x8 1500: 3100067f cmn w19, #0x1 1504: 54ffff21 b.ne 14e8 <__call_exitprocs+0x58> // b.any 1508: f9439f20 ldr x0, [x25, #1848] 150c: b4000140 cbz x0, 1534 <__call_exitprocs+0xa4> 1510: b9400aa1 ldr w1, [x21, #8] 1514: f94002a0 ldr x0, [x21] 1518: 350005a1 cbnz w1, 15cc <__call_exitprocs+0x13c> 151c: b4000580 cbz x0, 15cc <__call_exitprocs+0x13c> 1520: f9000340 str x0, [x26] 1524: aa1503e0 mov x0, x21 1528: d503201f nop 152c: f9400355 ldr x21, [x26] 1530: b5fffd35 cbnz x21, 14d4 <__call_exitprocs+0x44> 1534: a94153f3 ldp x19, x20, [sp, #16] 1538: a9425bf5 ldp x21, x22, [sp, #32] 153c: a94363f7 ldp x23, x24, [sp, #48] 1540: a9446bf9 ldp x25, x26, [sp, #64] 1544: a94573fb ldp x27, x28, [sp, #80] 1548: a8c77bfd ldp x29, x30, [sp], #112 154c: d65f03c0 ret 1550: b9400aa0 ldr w0, [x21, #8] 1554: f9400a82 ldr x2, [x20, #16] 1558: 51000400 sub w0, w0, #0x1 155c: 6b13001f cmp w0, w19 1560: 54000220 b.eq 15a4 <__call_exitprocs+0x114> // b.none 1564: f9000a9f str xzr, [x20, #16] 1568: b4fffc82 cbz x2, 14f8 <__call_exitprocs+0x68> 156c: 910442a0 add x0, x21, #0x110 1570: b9420001 ldr w1, [x0, #512] 1574: 1ad322c3 lsl w3, w22, w19 1578: b9400abc ldr w28, [x21, #8] 157c: 6a01007f tst w3, w1 1580: 54000161 b.ne 15ac <__call_exitprocs+0x11c> // b.any 1584: d63f0040 blr x2 1588: b9400aa0 ldr w0, [x21, #8] 158c: 6b1c001f cmp w0, w28 1590: 54fff9c1 b.ne 14c8 <__call_exitprocs+0x38> // b.any 1594: f9400340 ldr x0, [x26] 1598: eb15001f cmp x0, x21 159c: 54fffae0 b.eq 14f8 <__call_exitprocs+0x68> // b.none 15a0: 17ffffca b 14c8 <__call_exitprocs+0x38> 15a4: b9000ab3 str w19, [x21, #8] 15a8: 17fffff0 b 1568 <__call_exitprocs+0xd8> 15ac: b9420401 ldr w1, [x0, #516] 15b0: f9408a80 ldr x0, [x20, #272] 15b4: 6a01007f tst w3, w1 15b8: 54000121 b.ne 15dc <__call_exitprocs+0x14c> // b.any 15bc: aa0003e1 mov x1, x0 15c0: b9406fa0 ldr w0, [x29, #108] 15c4: d63f0040 blr x2 15c8: 17fffff0 b 1588 <__call_exitprocs+0xf8> 15cc: aa1503fa mov x26, x21 15d0: aa0003f5 mov x21, x0 15d4: b5fff815 cbnz x21, 14d4 <__call_exitprocs+0x44> 15d8: 17ffffd7 b 1534 <__call_exitprocs+0xa4> 15dc: d63f0040 blr x2 15e0: 17ffffea b 1588 <__call_exitprocs+0xf8> 15e4: 00000000 .inst 0x00000000 ; undefined 00000000000015e8 <_exit>: #include "xil_types.h" /* _exit - Simple implementation. Does not return. */ __attribute__((weak)) void _exit (sint32 status) { 15e8: 14000000 b 15e8 <_exit> Disassembly of section .init: 0000000000001600 <_init>: 1600: a9bf7bfd stp x29, x30, [sp, #-16]! 1604: a9bf73fb stp x27, x28, [sp, #-16]! 1608: a9bf6bf9 stp x25, x26, [sp, #-16]! 160c: a9bf63f7 stp x23, x24, [sp, #-16]! 1610: a9bf5bf5 stp x21, x22, [sp, #-16]! 1614: a9bf53f3 stp x19, x20, [sp, #-16]! 1618: a8c153f3 ldp x19, x20, [sp], #16 161c: a8c15bf5 ldp x21, x22, [sp], #16 1620: a8c163f7 ldp x23, x24, [sp], #16 1624: a8c16bf9 ldp x25, x26, [sp], #16 1628: a8c173fb ldp x27, x28, [sp], #16 162c: a8c17bfd ldp x29, x30, [sp], #16 1630: d65f03c0 ret Disassembly of section .fini: 0000000000001640 <_fini>: 1640: a9bf7bfd stp x29, x30, [sp, #-16]! 1644: a9bf73fb stp x27, x28, [sp, #-16]! 1648: a9bf6bf9 stp x25, x26, [sp, #-16]! 164c: a9bf63f7 stp x23, x24, [sp, #-16]! 1650: a9bf5bf5 stp x21, x22, [sp, #-16]! 1654: a9bf53f3 stp x19, x20, [sp, #-16]! 1658: a8c153f3 ldp x19, x20, [sp], #16 165c: a8c15bf5 ldp x21, x22, [sp], #16 1660: a8c163f7 ldp x23, x24, [sp], #16 1664: a8c16bf9 ldp x25, x26, [sp], #16 1668: a8c173fb ldp x27, x28, [sp], #16 166c: a8c17bfd ldp x29, x30, [sp], #16 1670: d65f03c0 ret