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White Paper: Cortex-M for Beginners - An overview of the Arm Cortex-M processor family and comparison

Ping Zuo 左平
Less than one minute read time.

by Joseph Yiu

Abstract

The Arm Cortex-M family now has five processors. In this paper, we compare the features of various Cortex-M processors and highlight considerations for selecting the correct processor for your application. The paper includes detailed comparisons of the Cortex-M instruction sets and advanced interrupt capabilities, along with system-level features, debug and trace features, and performance comparisons.

Update 21 June 2017

Since writing this block we have announced further additions to the Cortex family, Cortex-M23 and Cortex-M33, and updated the document. The latest version is available here: Cortex-M for Beginners - An overview of the Arm Cortex-M processor family and comparison (2017).

Arm Cortex-M23 and Cortex-M33 are the first embedded processors using  the Armv8-M architecture, bringing the proven secure foundation of Arm TrustZone to the most constrained IoT nodes.

Download the White Paper - Cortex-M for Beginners

White Paper - Cortex-M for Beginners - 2016 (final v3).pdf
Anonymous

  • Hi Ashar,

    Exception numbers are from #0 to #255 in current Cortex-M designs..

    However, #0 to #15 are reserved for system exceptions inside the processor, and exception #16 to #255 (named as IRQ #0 to IRQ #239).

    - Exception #16 = IRQ#0

    - Exception #17 = IRQ#1

    ...

    Currently, only part of the reserved system exceptions are utilized:

    Exception #2 - Non-Maskable Interrupts

    Exception #3 - HardFault

    Exception #4 - MemmangeFault (Armv7-M / Armv8-M Mainline)

    Exception #5 - BusFault (Armv7-M / Armv8-M Mainline)

    Exception #6 - UsageFault (Armv7-M / Armv8-M Mainline)

    Exception #7 - SecureFault (Armv8-M Mainline)

    Exception #11 - SVCall

    Exception #12 - DebugMonitor (Armv7-M / Armv8-M Mainline)

    Exception #14 - PendSV

    Exception #15 - SysTick timer

    As a result of these internally reserved exception types, IRQ number only go up to #239 in Cortex-M3/M4 and M7.

    Thanks Carlos and Goodwin for the additional information :-)

    regards,

    Joseph

  • Hi Carlos,

    The link in your reply is pointing to

    Arm Cortex™-M Programming Guide to Memory Barrier Instructions

    Application Note 321

    section 4.2. Nested Vectored Interrupt Controller of Cortex-M4 Devices Generic User Guide can be found here

    http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/CIHIGCIF.html.

    Regards,

    Goodwin

  • Cortex-M devices have only 240 (ie 0-239) vectors interruptions, each with 256 priority levels (0 to 255).

    see this section "4.2. Nested Vectored Interrupt Controller" in the Cortex-M4 Devices Generic User Guide, the other Cortex-M series are equal.

    I do not know the answer why the NVIC only handles interrupts and exceptions between 0 and 239 and really ignores the other 240-255, these values are used internally?

  • Thanks - it is a very well written article.   I have some questions:

    1.  Figure 8:  Exception Type column - at the top you have 239.  Am I correct that it should be 255?

    2. Is the the term INT # same as IRQ # ?

    Thanks.

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