Arm Community blogs

Wow it's that time again; our 4th release of Ubuntu on ARM is upon us. In the past we have provided a Freescale iMX51 image, a Marvell Dove image and a TI OMAP 3 image for Beagle Boards. This cycle…

This post is part of a series:Condition Codes 1: Condition Flags and CodesCondition Codes 2: Conditional ExecutionCondition Codes 3: Conditional Execution in Thumb-2Condition Codes 4: Floating-Point Comparison…

In the last article, I explained how to modify SWP code to make use of compiler intrinsics.  Using intrinsics hides the underlying detail needed to use the load and store exclusive instructions (LDREX…

Before ARMv6, the main synchronisation mechanism was the SWP instruction. SWP has two aspects, in a uniprocessor system it allows the read and write operations not to be interrupted between them.   In…

Once you move beyond short sequences of optimised Arm assembler, the next likely step will be to managing more complex, optimised routines using macros and functions.

This post aims to provide a simple introduction to Arm assembly language.

Ideally caches act as magic make-it-go-faster logic sitting between processor cores and memory banks. But there are cases where cache behaviour must be considered to get the desired result.

This is the first part of a series on how to write SIMD code for Neon using assembly language. It covers getting started with Neon, using it efficiently, and more.

Sitting in the airport at the end of a week's business trip to the US, I reflected back on the week.  It turned out that my colleague on this trip has an even worse sense of direction than myself.…