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ARM and Keil Tools

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Chinese Version 中文版: Cocos Code IDE 1.1.0:集成ARM DS-5,高效调试C++

As an important product of the Cocos Developer Platform, Cocos Code IDE has finally brought to us its version 1.1.0integrating with ARM DS-5 and enabling efficient C++ debugging. In this new version, Cocos Code IDE has possessed authorization from ARM® to issue ARM Development Studio 5DSTM-5Community Edition, aiming at further smoothening the development process and enhancing user experience.

 

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DS-5 is a powerful tool chain that has integrated many ARM-exclusive features into Eclipse platform; based on Eclipse development environment, DS-5 offers superior window management, project management and C/C++ source code editing tools, and supports C++ developing and debugging on Android devices.

 

In version 1.1.0, granted by ARM, Cocos Code IDE is motivated to offer great help and convenience to developers by providing DS-5 Community Edition for free.

 

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Cocos Code IDE is a cross-platform IDE based on Eclipse, especially for Cocos2d-x Lua & JavaScript developers. With IDE, developers can easily create game projects, compile code and debug on different platforms. Moreover, developers are able to check the effect real time and in the end publish a ready-to-go package.

 

At the moment, ARM DS-5 Community Edition has been perfectly integrated into Cocos Code IDE as well as its cool feature of C++ code debugging on Android device, meaning that you can debug game logic written with script languages or C++ in the same environment. At the same time, DS-5 provides a C++ development environment for Cocos Code IDE, so that developers can now develop some key or sensitive logic with C++, and then compile, pack and debug on Android devices.

 

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DS-5 Community Edition tool kit, based on Professional Edition, provides necessary debugging and system analysis to create reliable and highly optimized applications for devices based on ARM processor without complexity and inefficiency that are often found on the scattered open source tools. With DS-5, Cocos Code IDE is equipped with a powerful C++ code debugging on Android platform feature, supporting debugging on Android devices based on ARM9/ARM11 and Cortex®-AARMv7-Aprocessor architecture. The efficient debugging of C++ logics will greatly accelerate the Android application development process.

 

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Android platform performance analysis is another highlight of Cocos Code IDE 1.1.0. Developers just need to click “Start Capturing” in the data view of ARM Streamline to collect information of the target for analysis and click “Stop” to check the Performance Analysis Report when the analysis is finished. Simple GPU / CPU functional analysis will list out the key information like the most time-consuming code segments, the most time-consuming function lists, etc. lowering the burden of GPU/CPU and uplifting the user experience.

 

The world of mobile Internet is changing dramatically every day, and so is the mobile development technology. Cocos Code IDE focuses on script game development based on Cocos2d-x engine, and is motivated to enable a smoother and faster development process and a better development experience; Cocos Code IDE also actively embraces opportunities to combine advanced features from others to help developers gain a favorable position in this rapidly changing market.

 

Chinese Version 中文版: 使用DS-5从FVP中收集Trace数据

One of the new features for ARM DS-5 Development Studio in v5.20 is instruction trace for our Fixed Virtual Platform (FVP) simulation models. This enables you to capture a trace of program execution in the models that are included by default in DS-5: an ARMv7 FVP (in Professional Edition and Ultimate Edition) and ARMv8 FVP (in Ultimate Edition). If you want to try it out, you can download DS-5 Ultimate Edition and generate a 30-day eval license.

 

What is trace and why is it useful?

 

Trace is the continuous collection of information which represents the execution of software on a system. In real hardware, it is non-invasive, meaning it doesn't slow a processor down. The raw trace data is highly compressed and must be decompressed to be useful. In the case of DS-5, it helps us to see the proportion of time spent in a function, along with the machine instructions which were executed at any point in the trace capture. ARM's debug and trace infrastructure is called CoreSight (which is not modeled directly in our Fast Models and FVPs).

 

It is used at every stage of a design process, from modelling the system through to in-field failure analysis. Trace is particularly useful for bare-metal or Linux kernel debugging.

 

Since ARM Fast Models and FVPs are instruction accurate, collecting instruction trace is a natural extension to the debug functionality that DS-5 already provides for models, making the experience as close as possible to writing software for a real device. It's important to remember that Fast Models and FVPs are not cycle accurate, so the actual time it takes to execute a function won't correlate with the time it would take on the real silicon (though the proportion of time spent in that function would remain fairly consistent). Now that debug configurations have been added for the three previously mentioned FVPs, it’s easy to use it in practice. Currently, there is no support for adding trace to other models in DS-5 or for collection of data trace (where address and register values are also recorded from load and store instructions). Edit - if you have your own Fast Model based platform and would like to see trace supported on it in DS-5, then please contact ARM.

 

Making use of model trace

 

You will notice in the DS-5 Debug Configurations panel that model trace is only available for bare-metal and Linux kernel debug connections. Trace isn't the right solution for debugging Linux applications, as the extra level of complexity that an OS adds would mean sifting through an unmanageable amount of trace data.

 

Model-Trace-Debug-Configuration.png

 

The best way to test out model trace is to import an example. There are bare-metal examples for everything from simple Hello World programs to more complex RTOS programs. In the example below, I've imported the "traffic lights" program which runs on the Keil RTX RTOS.

 

All of our FVP bare-metal examples have been reconfigured to collect model trace, but you can also use your own images. Once trace is configured, it behaves exactly like trace on real hardware, using the same trace view in DS-5.

 

Our trace is being collected into a circular buffer. This is fairly common in ARM SoCs, which use an Embedded Trace Buffer (ETB) to collect a record of software execution, which is constantly overwritten and refreshed (or alternatively, just filled once).

 

Trace will start automatically whenever you run through a debug session, unless you set trace start and stop points manually. This can be useful for just tracing the function that you’re interested in. In the screenshot below, you can see the trace collected on start-up of the RTX Traffic Lights example (which was set to debug from main):

 

Model-Trace-Initial-Collection.png

 

It’s important to note that DS-5 doesn't automatically overwrite the contents of the trace view each time you collect more trace. If you've set trace start and stop points, clearing the trace view before running will show only the trace between these two points. In this example, I've started collecting trace when the traffic light timer is between the defined start and end times that the user sets in the program.

 

Model-Trace-Start-Point.png

 

How does model trace work?

 

Model trace isn't a direct model of CoreSight. Instead, it collects model events (instructions executed and exceptions) directly. DS-5 then interprets this and displays it in the same trace view used for CoreSight trace. Model trace will slow down the execution of the model on your host machine, unlike a real life system, where the CoreSight infrastructure reports trace non-invasively.

My family are American, and this is a time of year when their thoughts turn towards the family and friends in the USA who are celebrating the Thanksgiving holiday.  For me, late November also happens to coincide with the biannual release of Fast Models.

 

It has been a busy six months for the team who have been working on a wide and varied range of models, as well as new functionality and product enhancements.  As you can infer from the the title, there has been a big emphasis on Cortex-M class models in this release cycle.  Although the majority of Fast Model licensees are deploying them into platforms utilizing the Cortex-A models, there is a sizable contingent of users for the Cortex-M family as well.  Cortex-M7 is the recently announced high-end micro-controller, whereas Cortex-M0 and Cortex-M0+ are more mature cores with very small footprints.  From a modelling point of view they both leverage the new Cortex-M architecture model which will also form the basis of other new models to be announced in 2015.

 

There are several other new models being made available alongside this release, for Media and System IP products.  These are available to lead partners, and will be in due course introduced to the standard portfolio.

 

Outside of the new models, the main focus for work in this release has been around performance improvements.  There have been three aspects to this: improvements to the underlying simulation engine, improvements in the bridges to SystemC and improvements in the way that Fast Models interacts with the host workstation keyboard and mouse.  The results of this work - and it's an ongoing task to maintain performance as the systems being simulated become more complex - will yield benefits for most partners and most applications.

 

We also added support for Visual Studio 2013 and gcc 4.7.2 as tool chains for building the simulation platforms.  Leveraging newer compilers also provides performance improvements as they generate more optimal code.

 

Another area that has been worked on is on the link with the ARM DS-5 tool suite.  The latest release of DS-5 (5.20) provides support for viewing trace information generated by a Virtual Platform with Fast Models.

 

2014 was a a busy year, both in product development and supporting the rapidly growing adoption of Virtual Prototypes as part of the SoC development process.  Our ecosystem partners have continued to integrate Fast Models into their solutions in a variety of ways.  One that has generated a lot of interest in 2014 has been "Hybrid" virtual platforms, otherwise known as co-emulation.  In these a processor subsystem running in the virtual prototype is bridged to an emulator which is used to simulate other parts of the system. A typical scenario would be for platforms that have a GPU.  The hybrid approach has yielded impressive performance gains for simulating these complex systems.

 

You can get an overview of what we are talking about here (a joint presentation with Cadence at the ARM TechCon last month): Reducing Time to Point of Interest With Accelerated OS Boot

 

Now have a moment or two to draw breath before diving into the development cycle for the 2015 releases.  We have a full road map of new products to model, a focus on providing more hooks in the models for profiling the software running on them and of course, the ongoing performance work.

 

Happy Thanksgiving!

R for Real-time

We are very excited to have partnered with Renesas Electronics to introduce support for the recently announced Renesas RZ/T1 product series in ARM DS-5 Development Studio. The new device family comprises ten ARM Powered® products aimed at industrial applications that require both high performance and real-time predictability. Based on an ARM® Cortex®-R4 processor operating at up to 600 MHz, the product line also includes configurations that feature a Cortex-M3 core to enable highly integrated asymmetrical multi-processing (AMP) applications. Visit Renesas website (English/Japanese) if you want to learn more about the RZ/T1 series.

 

Renesas RZ/T1 in DS-5

ARM DS-5 is a complete software development tools solution for RZ/T1 users. It includes efficient C/C++ code generation for both ARM cores and full support for synchronous and asynchronous AMP debug.

 

Some benefits of DS-5 for RZ/T1:

  • ARM Compiler 5: industry reference C/C++ compiler for Cortex-R4 and Cortex-M3 processors, compatible with the widest range of RTOS, middleware and third-party tools
  • Simultaneous debug connections to both ARM processors
  • Collection, decode, synchronization and visualization of trace data from ARM CoreSight™ ETM (Embedded Trace Macrocell) and ITM (Instrumentation Trace Macrocell) units for faster bug finding
  • TÜV SÜD certified compiler and compiler qualification documentation for functional safety certification
  • Built-in OS awareness for leading commercial real time operating systems (RTOS)


Renesas-RZT1-configDB.PNG



Target connections for your every need

Depending on the stage you are in the software development project and your budget, you may select different technologies to connect DS-5 to your RZ/T1 target. See below summary of the target connection options, for you to pick the right one for your needs.

 

Target connection typeBest forTrace capture
DSTREAMBoard bring-up, high-performance debug and ETM trace-based analysis

off-chip (4 GB DSTREAM)

on-chip (4 KB ETB)

ULINKproFast software debug with on chip trace  (Note: ULINKpro trace is not supported in DS-5)on-chip (4 KB ETB)
ULINKpro DFast software debug with on-chip traceon-chip (4 KB ETB)
ULINK2Basic software debugon-chip (4 KB ETB)
CMSIS-DAPSilicon evaluation on development boards (USB connection to board, no debug hardware required)on-chip (4 KB ETB)

Renesas-RZT1-target-connection.png

 

Availability

RZ/T1 platform configuration file is available for DS-5 version 5.20 users upon request. If you require access to it now, get in touch.

Hi, It would be really useful for the team here at ARM, if you could have a few moments to complete a short survey of your experiance with Juno ARM's Development Platform for ARMv8. I can feed this back into the requirements for future plaftoms and also try to address any issues you incountered either with the software or hardware. Click here to complete survey

 

Thanks,

Liam

ARM releases updates to DS-5 on an approximate quarterly cadence, and as I write this, we have just released v5.20 of the tool. With each release we increment the debugger and compiler(s) version to the latest version available. This can cause difficulty for the compiler use case, as typically the version of a compiler used for a given project becomes fixed at some point in time, and moving from this version becomes costly from a validation and/or qualification point of view. ARM has always made the ARM Compiler package available as a separate installation for those users that do not wish to use the default version. However, until now, it has been precisely that... a separate installation, detached from the rest of your DS-5. As you've likely guessed from the title of this article, this is a situation that we have improved within DS-5 v5.20.

 

You will first need to download the appropriate compiler package, and install. I recommend installing to the DS-5 sw directory where the default tools are, though you can use any location. You then need to make DS-5 aware of this installation. To do this, launch the Eclipse GUI, and navigate through the Window menu to Preferences. Therein, drill down the left hand side to select DS-5, and then Toolchains:

 

preferences1.png

 

Click Add... and navigate to the bin (or bin64) directory of the compiler you wish to add:

 

preferences2.png

 

Click on Next and the tools will verify the location:

 

preferences3.png

 

Click on Finish, and you will be asked to restart the GUI. The newly added compiler version will now be available to use in your projects:

 

newproject.png

 

For those that build from makefiles or equivalent, these changes are reflected in the DS-5 Command Prompt. Now, when you launch this, you will first see the following:

 

command_prompt1.png

We have created an add_toolchain script that behaves in a similar manner to the above. Use the path to the bin directory and it should work just as above.

command_prompt3.png

We provide two scripts (select_toolchain and select_default_toolchain) to allow the user to set the appropriate compiler version that they wish to use. As the names suggest, using select_default_toolchain is a do-once operation to set the default compiler version used each time the user launches the command prompt. If necessary, you can then override the compiler version used for a particular compilation session using select_toolchain. The use of either of these options is simple. Call the appropriate script, and you will see a list of available compiler versions. Select the version you wish to use, and the environment will instantly be set to point to that version.

 

command_prompt2.png

Join us for a live webinar on Monday 10th November 10:00 am PST (1:00 pm EST, 6:00 pm GMT) to learn about the new features of CMSIS v4. This will be hosted by Christopher Seidl, Keil MDK Technical Marketing Manager.

 

The Cortex-M Microcontroller Software Interface Standard (CMSIS) is a vendor-independent standard for hardware manufacturers and tool vendors. It provides common software layers and interfaces for all microcontrollers based on ARM Cortex-M processors.

 

In this webinar you’ll learn about the recently released CMSIS 4, which includes several major improvements that will affect embedded developers in the near future. It adds a standardized driver interface for Middleware and user applications (CMSIS-Driver) and Software Packs for device and board information as well as the delivery of software components.

 

Take away from this webinar a deeper understanding of CMSIS 4 and how it can be used to speed-up the software development process. All parts of CMSIS will be covered and code examples will be used to demonstrate ease-of-use.

 

Register for your place »

 

CMSISv4.png

For the last TechCon, my colleage Bob Boys has created a comprehensive application note that tells you how to create a middleware applications using CMSIS-Drivers and our middleware that comes with Keil MDK-ARM Professional. You'll learn how to start a project from scratch, adding features as you go. The application note explains how to setup, debug and run a CMSIS-compliant application using CMSIS-RTOS RTX, USB and graphic display capabilities. It uses the STMicroelectronics STM32F429IDISCOVERY kit, but works similarly with all ARM Cortex-M based microcontrollers and development boards that have CMSIS-Drivers available (for example the MDK5 - KeilMCB1800 based on NXP LPC1857).

 

Check out the application note on the Keil website: Application Note 268: Creating a CMSIS Middleware Application

Happy Friday!! This week is over and that is a beautiful thing. I am going to celebrate finishing my operating systems midterm by answering a rtx question today.


This week is from the Connected Community:


"Hi Experts,

 

There is code pieces on Full context and reduced context in the RTX code.

 

What this is actually intended for ?"

 

Full context Vs Reduced Context  techguyz

 

 

There are 2 types of task switch in RTX library for ARM7 and ARM9: reduced context switch and full context switch.

Reduced context switch does not store all registers to the stack on task switch. The advantage of this move is to make the system more efficient in that the switch is faster and requires less space on the stack. Some functions that utilize this type are os_tsk_pass, os_dly_wait, os_sem_wait, etc.

Then there is the full context switch that stores all registers to the stack. This task switch is slower and needs more space on the stack, ideal for swithces with timeouts (i.e. round robin). Some of the functions that utilize the full context are os_dly_wait and isr_evt_set.

Since the rate of the context switch can make or break a real-time operating system's ability to process efficiently, RTX takes advantage of the reduced context to save time wherever possible and full context in functions where the register contents are too critical to omit.


It's also worth noting that this is not relevant for Cortex-M processors, which use the CMSIS-RTOS compliant version of RTX. 

 

References:

MCB2300 Influence of TCPnet on RTX scheduler

TestPCF8563.rar RTX_Config.c

For some time msr and mrs works on CP15 registers, so instead of using the cryptic

 

mrc p15,0,r0,c0,c0,5    ; hint: r0 = MPIDR





 

it can be as simple as

 

mrs r0,MPIDR






Unfortunatley, it just works for 32 bit registers. For 64 bit registers there is still just mcrr and mrrc

So here is a macro that solves this:

So here is a macro that solves this:

 

;-----------------------------------------------------------------------
    macro
    m__op64 $op,$reg0,$reg1,$coproc,$opcode,$crn
        $op $coproc,$opcode,$reg0,$reg1,$crn
    mend


;----------------------------------------------------------------
    macro
    m_op64 $sReg,$op,$reg0,$reg1
        IF ("$sReg" = "PAR")
            m__op64 $op,$reg0,$reg1, p15,0,c7
        ElIF ("$sReg" = "TTBR0")
            m__op64 $op,$reg0,$reg1, p15,0,c2
    ; .....
    ; ..... add more regs here
    ; .....
        ELSE
            INFO 42,"$sReg"
            ASSERT {FALSE}
        ENDIF
    mend


;----------------------------------------------------------------
    ; "m_msrr" works like "msr", but puts two core regs into one
    ; 64 bit reg
    macro
    m_msrr $sReg,$reg0,$reg1
        m_op64 $sReg,mcrr,$reg0,$reg1
    mend


;----------------------------------------------------------------
    ; "m_mrrs" works like "mrs", but puts one 64 bit into two
    ; core regs
    macro
    m_mrrs $reg0,$reg1,$sReg
        m_op64 $sReg,mrrc,$reg0,$reg1
    mend




 

So now you can write things like

 

  m_mrrs r0,r1,PAR
  m_msrr TTBR0,r0,r1




 

And one day, when armasm implements msrr and mrrs all it take is removing the "m_" there.....

TUV-1.png

Join us for a live webinar on Wednesday 22nd October 1:00 pm EDT (10:00 am PDT) to learn how ARM tools can be used more widely for safety-related development, now that the ARM Compiler toolchain is fully certified by TÜV SÜD, a recognized safety industry expert. This will be hosted by Daniel Owens, ARM Compiler Product Manager, and Johannes Bauer, Keil MDK Product Manager.

 

The webinar will feature the TÜV certified ARM Compiler and Qualification Kit, support for coding standards and code coverage in Keil MDK. This enables anyone deploying ARM products into a variety of safety-related sectors (for e.g. automotive, industrial control, railway, aerospace and medical), to reduce risk and gain confidence that the system is functioning according to design.

 

The TÜV certified compiler and compiler Qualification Kit are now part of both Keil MDK-ARM Professional Edition and DS-5 Development Studio Ultimate Edition.

 

 

Register for your place »

We've been showcasing the latest and greatest tools for ARM software development over the last couple of days at TechCon 2014 in Santa Clara. It's been a busy week, with plenty of announcements from our friends at ARM Mali Graphics and mbed along with lots of questions and feedback from engineers already using our tools.

 

Here's my summary of what we've been demonstrating or announcing this week in the world of tools:

 

DS-5 Development Studio

We've been using DS-5 Development Studio Ultimate Edition coupled with DSTREAM for JTAG debug and trace of the Cortex-A53x4 and Cortex-A57x2 based Juno Development Platform. DS-5 handles connections to individual cores, clusters or the whole system, depending on what you want to target. Upcoming changes to the registers view allow you to easily see the split between AArch64 and AArch32 registers, whilst the disassembly and trace views handle ARMv8 instructions just as they had previously handled earlier instruction sets. Many of our visitors asked about the debugging experience of ARMv8, so it was great to be able to show the jump from AArch64 to AArch32 when launching 32-bit apps such as Angry Birds on our 64-bit Android OS.

 

DS-5 has now been around for over 4 years, so we spend a lot of time at events like this catching up with customers who have been successfully developing ARM software using our tools. It's been great to hear feedback from DS-5 users and a lot of fun showing off the features that our engineering teams have worked hard to develop since the previous TechCon. If you're a DS-5 user, I encourage you to sign up to our monthly developer newsletter, which shows you how to use each new feature to solve every day programming problems.

 

Streamline and OpenCL for NEON

Streamline has always been a popular tool with engineers at exhibitions across the world and TechCon has been no different. With counters to support ARMv8 profiling, as well as a slick live capture mode, Streamline is now a firm favorite for system optimization with software development studios.

 

One of the announcements this week was around OpenCL support between GPU and CPUs with NEON, using Streamline to demonstrate the dependencies. This is a great extension of the OpenCL mode that we released earlier this year and should help to make compute processing a whole lot easier for developers. Read more here: Heterogeneous Multiprocessing Gets a Boost with the New OpenCL for NEON Driver

 

Keil MDK-ARM v5

Reinhard Keil was here this week to show off new features in MDK, including the software packs concept, demonstrating how easy it is to carry out microcontroller software development when you have access to the extensive range of middleware that is included in the packs. Along with Bob Boys, Reinhard delivered a training session to explain the concept of CMSIS-Drivers in order to create a USB application faster using the CMSIS software framework. 

 

V Certified Compiler

Another exciting announcement this week is that we are including a certified version of ARM Compiler 5, with long term support in MDK Professional and DS-5 Ultimate Edition. This makes software development for safety critical applications easier in both tools, especially for IEC 61508 and ISO 26262. We also include the ARM Compiler Qualification Kit to assist you in making your compliance case. This struck a chord with a lot of developers who were working on automotive software projects who dropped by the booth, so we hope it will be useful to many of you.

 

Fast Models and Fixed Virtual Platforms

Rob Kaye was on hand to deliver a great set of demos showing the integration between ARM Fast Models and DS-5. With model trace and Streamline for models in development, he gave visitors a glimpse into the future of models and was kept busy both days by the number of engineers already using models for ARM software development.

 

Of course, there have been new features and announcements from all of the software tools providers in our ARM ecosystem. My colleague Andy Frame (@andyframe_ARM) took on the role of roving reporter this week to cover their exciting news. Check out his blog here: Day 1 of TechCon 2014 with Simon Segars, Atmel MCUs, Freescale Kinetis, STMicroelectronics STM32 F7, HP Moonshot, Dell s…

 

What did you think?

Were you at TechCon? Did you come and visit any of the ARM software tools teams? Let us know what you thought in the comments below... and see you all next year!

Freescale will be hosting their Design with Freescale event in São Paulo on October 8th, and I will be there to support the technology sessions and the Technology Lab, demonstrating ARM's software tool solutions that support all of Freescale's ARM based Portfolio.

 

As you likely know if you are reading this, ARM is ubiquitous in the industry from sensors to servers. Freescale similarly offer ARM based products, from Kinetis MCUs, through the Vybrid and i.MX series of Application processors, to advanced Layerscape Networking solutions.

 

ARM tools support these devices with Keil MDK toolchain and DS-5 Development Studio as appropriate. Furthermore there are a variety of Freescale platforms supporting the mbed Development Platform.

 

Also at the event, my colleague Drew Barbier will talk about the ARM Accredited Engineer (AAE) program. This is a run-through of the subject matter covered by the ARM Accredited MCU Engineer accreditation, focusing on software aspects of the ARMv-6M and ARMv7-M Microcontroller architectures as implemented in the Cortex-M processor family. Drew will offer a look into the subject matter needed for the exam, in order to benefit from the industry-recognized qualification.

 

I look forward to meeting you there!

Visit us at the ARM Techcon in USA or at the Conference for ARM-Systems in Germany to learn about the new innovations for Cortex-M microcontrollers and the related CMSIS software standard.

 

Santa Clara, USA, October 1 - 3, 2014

The ARM TechCon 2014 in Santa Clara is a great event to get the latest information about the Cortex-M processors and the numerous microcontroller families that are based on that processor technology.

 

Visit the ARM booth for an in-dept demonstration of the Keil MDK Microcontroller Development Kit Version 5 that incorporates the Run-Time Environment (RTE). With RTE you compose sophisticated software frameworks for your embedded application from pre-built CMSIS and middleware software components.

 

Don't miss on October 2, the session Create an USB Application Using CMSIS-Drivers. In this TechCon conference session you will learn the benefits of CMSIS-Driver for creating microcontroller applications. During a 50 minute training session, Bob Boys and Reinhard Keil explain the concept of the CMSIS-Drivers. An example USB application shows how CMSIS-Drivers help to create embedded applications for supported Cortex-M microcontrollers faster by using the industry standard CMSIS software framework. The first 30 attendees registered to that TechCon workshop will get a complementary evaluation board and a full 60-day license for MDK-Professional which allows you to replicate the projects.

 

Munich, Germany, October 8 - 9, 2014

The Konferenz für ARM-Systementwicklung" in Munich is just one week after the ARM TechCon. This event is a great opportunity to get the latest update from ARM specialists and other ARM partners. Dr. Krisztian Flautner, Vice President Research & Development ARM, presents on 9. October 2014 his keynote on the topic Internet of Things and explains how this applies to industrial and automotive applications.

 

Other ARM speakers at this event cover the following topics:

  • Cortex-M – The best fitting architecture for my application: Dr. Ian Johnson
  • CMSIS – faster Software Development using software components such as DSP Library: Christopher Seidl
  • Benchmarking of Microcontrollers: Joseph Yiu
  • ARM big.LITTLE Technology: Why? What? How?: Kinjal Dave
  • Real-time hypervisors for safer control systems: Chris Turner
  • Building High End, Low Power Wearable SoCs using Application Processors: Kinjal Dave

Last month I covered the details of using ARM Compiler 6 to compile bare metal software included in Carbon Performance Analysis Kits (CPAKs) for ARMv8 processors such as the Cortex-A53. This time I will outline the flow used to connect ARM DS-5 version 5.19 to debug software. DS-5 is a full set of tools for end-to-end software development for ARM processors and includes the ability to connect to cycle accurate models running in SoC Designer and debug software.

 

Overview of DS-5 to SoC Designer Connection

 

Setting up SoC Designer for use with DS-5 involves the following steps:

  1. Use a DS-5 supplied program called cdbimporter to create a DS-5 configuration database.
  2. Add the configuration database to the list of systems to which DS-5 can connect.
  3. Create a DS-5 Debug Configuration which specifies the system to connect to and the software to debug.
  4. Connect to a SoC Designer simulation using the Debug Configuration to perform software debugging tasks.

 

This article presents a summary of the flow. The last two steps are common to debugging with eclipse, but the first two steps may be new to eclipse users. There is an application note in the SoC Designer release which provides additional information about cdbimporter. SoC Designer users can look at the file $MAXSIM_HOME/doc/DS5_App_Note.pdf

 

Generating a DS-5 Configuration Database

 

The database is created with a DS-5 utility called cdbimporter, which provides a number of useful features to help automate the process such as:

  • Query the host machine for running CADI servers
  • Identify the simulation of interest
  • Identify the cores included in the simulation
  • Generate the configuration database

 

I will use a Cortex-A53 Baremetal CPAK with SoC Designer 7.14.6 for reference.

 

a53x1 resized 600

To set up the DS-5 configuration database start the simulation as specified in the CPAK README file and load the software. Do not start running the simulation.

 

Run the simulation:

 

$ sdsim -b A53-cpak.conf -b $MAXSIM_PROTOCOLS/etc/Protocols.conf Systems/A53v8-MP1-CCI400.mxp

 

Then load the sorts_v8.axf file from the Applications/ directory and go to the shell prompt to run cdbimporter.

 

Setup the DS-5 shell environment using the path to your DS-5 installation:

 

$ /o/tools/linux/ARM/DS5_5.19/64bit/bin/suite_exec_ac6 bash

 

Now cdbimporter should be in the PATH and ready to run.

 

The output from cdbimporter is a directory containing the DS-5 configuration database which will be used in the next step.


Add the Configuration Database to DS-5

 

The next step is to make DS-5 aware of the new configuration database. Start by launching eclipse and set the workspace directory.

 

Import the database generated by cdbimporter as follows:
Open the Preferences page from the menu: Windows -> Preferences.
From the Preferences popup, select DS-5-> Configuration Database -> Add. The Add configuration database location dialog opens:

 

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Use the Browse button to navigate to the directory which contains the configuration database created in the first step.

 

Use the Name field to name this database for later identification in the Preferences (it can also be left blank).
Click OK to close the Add configuration database location dialog.
Click OK again to close the Preference window. You will see a dialog box indicating it is adding the new database.

 

The configuration database is now included in the DS-5 list of target systems.

 

Create a DS-5 Debug Configuration

 

The next step is to create a DS-5 Debug Configuration that creates the connection to the system to be debugged.

 

Start the DS-5 debug perspective as follows:

 

From the top menu, select Windows -> open perspective -> DS5 Debug.

 

From the top menu, select Run > Debug Configurations… (or right-click from the upper left “Debug Control” view and select debug configurations -> DS-5 Debugger).

 

From the “Debug Configurations” pop up, right-click on DS5-Debugger and select New.

 

On the Connection tab, close default groups, then scroll down and select the imported system; e.g., Carbon > A53-MP1-CCI400.mxp > Bare Metal Debug > Debug Cortex-A53_0

 

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On the Files tab select the .axf file of the application, in this case sorts_v8.axf.

 

Load symbols from file assumes you already loaded the application to debug from SoC Designer. To load the application from DS-5 instead, enter the name in the Application on host to download box and the application will be written to memory when the debugger connects.

 

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On the Debugger tab, in the Run Control panel, select "Connect only."

 

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Connect DS-5 to a SoC Designer Simulation and Debug Software

 

The final step is to launch the Debugger Configuration and connect to the SoC Designer simulation. You can do this immediately using the Debug button on the lower right of the Debug Configurations dialog.

 

You can also use the Debug Control tab by right-clicking on the connection and selecting “Connect to Target” from the context menu (shown below).

 

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After the debugger is connected the status is shown as “connected”:

 

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After connection, DS-5 can be used to debug the software running on the SoC Designer simulation.


Simulation on Another Machine or Port

 

If multiple simulations are starting and stopping there is a chance the port number the simulator is using is different than it was when the configuration database was created. The first simulation is normally port 7000, then the next is 7001. The numbers will recycle as simulations start and stop. It’s not necessary to start from scratch and create a new configuration database. There is an environment variable that is the easiest way to adjust to a new port number:

 

For bash I use:

 

$ export CADI_TARGET_MACHINE=localhost:7001

 

This environment variable can also be used to connect to a simulator on another machine by using the name or IP address of the machine which has the running simulation.


Conclusion

 

This summary covered the steps to connect DS-5 to SoC Designer. DS-5 is the best debugger to handle bare metal software for the AARCH64 state compiled with ARM Compiler 6 and DWARF4 debug information. Make sure to review the application note provided with each SoC Designer release for the latest information.

 

Jason Andrews

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