ARM University Program (AUP) and Xilinx University Program (XUP), together, organized a one-day workshop (ODW) on System-on-Chip (SoC) Design as part of their Faculty Development Program (FDP) initiatives in India on December 16, 2014. The workshop was collocated with IEEE’s International Conference on High-performance Computing HiPC 2014 in Goa, India. The participants were from all across India as well as neighboring Sri Lanka, representing a unique cross-section of universities from Ramdeobaba College of Engineering Nagpur, University of Moratuwa Sri Lanka, BITS Pilani Goa and Vellore Institute of Technology Chennai to BMS College of Engineering Bangalore, Indian Institute of Technology Kharagpur, DKTE Society’s Textile and Engineering Institute Ichalkaranji and RMK College of Engineering and Technology Chennai. The aim of the workshop was to showcase AUP’s flagship Lab-in-a-Box (LiB) on the first principles of SoC Design as a conceptual hands-on aid to faculty contemplating introducing SoC Design in a university curriculum. This particular LiB comprises of the ARM Cortex-M0 DesignStart Processor IP made available at no cost to university faculty through a EULA by ARM, Basys3 or Nexys4 FPGA boards donated by Xilinx, 100 licenses of Keil MDK Pro microcontroller software development tool donated by ARM and a full suite of teaching materials specially created for academics donated by AUP.
The workshop began with an introduction to SoC Design elucidating its three essential ingredients, namely, the processor core, the bus interconnect that stitches the peripheral interfaces and the interfaces themselves, such as UART and GPIO, to name a couple. The introduction included an overview of the ARM Cortex-M0 processor architecture and later touched upon the essentials of the AMBA 3 AHB-lite bus protocol. The ARM Cortex-M series of processor cores are all AHB-lite compliant. The participants marveled at how the specially pre-configured ARM Cortex-M0 DesignStart processor IP core made understanding and dealing with the AHB-lite signals incredibly simple, indeed building their confidence in this particular introductory-level SoC Design flow designed for academia. The explanation of the AHB-lite protocol was followed by an introduction to Artix-7 FPGA Architecture and an over-view of Vivado Design Flow the Artix7 FPGA chip on the Basys3 board requires for its configuration.
The introductions were immediately followed by a very basic lab – integrating LEDs on Basys3 with the IP core – for the proper learning and understanding of the Vivado Design Flow on Basys3, key to full and complete adoption of the SoC Design LiB in a university curriculum. The basic lab also involved integrating a peripheral memory block from which the processor IP core would fetch instructions. The more complex labs following lunch were made easy to follow through with a continually and gradually evolving flow. Side-by-side LED connectivity, first the UART interface had to be integrated for the purposes of establishing connectivity between a terminal window application, such as TeraTerm on a user laptop, and the SoC. A memory controller was simultaneously integrated for the purposes of managing the flash memory external to the Artix-7 FPGA on Basys3. Printf and Scanf functions were re-targeted to use the UART peripheral interface to input or output characters, enabling displaying of text messages and memory contents on the terminal window application for better debugging. With the UART interface in place and working, the next lab illustrated how to interrupt the processor core from a low-power mode. A character sent from the serial terminal of a user laptop through the UART interface generated the interrupt signal to wake up the processor core. After waking up, the processor core executed instructions to display the received character using the LEDs.
Discussions with the participants during the workshop revealed they were interested in developing and possessing the ability to design their own SoCs around a soft processor IP core such as the ARM Cortex-M0 DesignStart Processor IP. For, with this ability, they would be able to tailor SoCs to intended applications. That in turn would mean just the minimum necessary interfaces around the SoC, keeping designs simple and costs economical with fewer gates, lower power, simpler fabrication and easy debug.
The faculty participants, in response, were made aware that designing a SoC with the ARM Cortex-M0 DesignStart IP actually presents the possibility of taping out the SoC. That would further mean they could potentially expose their students and researchers to possible other areas, such as those in back-end design or silicon validation, verification and testing, which are otherwise harder to introduce in a university setting. The participants were also informed that, to help universities out with fabrication requests at affordable costs, service providers such as MOSIS in the US and EUROPRACTICE in Europe have made available special Multi-project Wafer (MPW) services.