By chris.wright and Rupal Gandhi
We are part of the team that recently taped out a finFET testchip. It was one of our team’s first experiences with finFETs and we saw firsthand the implementation differences from our familiar CMOS processes! We will cover these differences in a series of blogs.
As process nodes shrink and we move from planar transistors to finFETs, the number of DRC rules has increased exponentially. This brings a large number of challenges and constraints from the layout of standard cells to full chip place and route. One area of increased complexity that affects place and route is the periphery of the logic block.
Figure 1: Finishing cell requirements for 28nm and larger processes
Finishing cells are used to ensure the periphery of logic blocks meet all DRC rules. For 28nm and larger processes, the application of finishing cells is relatively straightforward. As shown in Figure 1 there is only one type of finishing cell needed, the ENDCAP. This cell is placed at the end of each row of standard cells. Typically only one type of ENDCAP cell is required for the entire design.
Figure 2: Finishing cell requirements for 20nm and smaller processes, including finFETs
In smaller geometries, three new finishing cell types are needed as shown in Figure 2. ENDCAPs are still required as they were inthe older processes. In addition, the top and bottom rows need to be filled with TBCAPs. All corners require a special one of two finishing cells; convex corners use CNRCAPs while concave corners use INCNRCAPs. For the TBCAPs, CNRCAPs and INCNRCAPs, two versions may be required. One version is used when the NWELL is on the top or bottom edge of the block (NWELL OUT) and another is used when the NWELL is not on the top or bottom edge of the block (NWELL IN). Ultimately all of these new finishing cells mean the logic blocks on the chip will be encapsulated in a set of finishing cells as shown in Figure 3.
Figure 3 : Encapsulation of logic cells for 28nm and larger on the left and 20 nm and smaller on the right
The enhanced finishing cells are specifically designed to meet fin boundary conditions and compact nwell enclosure rules for inFETs process. The finishing cells allow flexible placement while avoiding endpoly violations. The additional wide cut poly rule requirements at boundaries, poly coverage over the diffusion and implant width are covered using enhanced finishing cells.
Our next blog on finFET implementation will describe the uniform pitch requirement for finFET process technologies.
Without going into details of foundry rules, across all foundries the poly must be cut and/or terminated appropriately in order to successfully print the layer. The nice thing is that users can select the appropriate "finishing" cell from the library, and this will be taken care of. The concern is just at block edges and vertices.
What are endpoly violations and why are they of importance? Thanks for your help on this, I'm still coming up to speed on finFETs.
All of the special cells will vary by finFET process. However, all of these processes will require proper termination of fins, poly and wells. This is what drives the need for the different types of finishing cells.