Interesting article on Semiconductor Engineering where options other than increasing clock frequency are considered for improving performance and data throughput of advanced node devices:
Our approach is to provide the 'different IP' as suggested in the article. On the advanced nodes, performance optimisation schemes require conditions to be accurately monitored on-chip and within the core. We have the belief that PVT conditions should be monitored and sensed by small analog sensors such as accurate temperature sensors, voltage monitors (core and IO) and process monitors. Quite simply, the more accurate you sense conditions the more watts can be saved for both idle leakage and active states of a device. For example, our embedded temperature sensors have been developed to monitor to a high accuracy for this reason. Once you have the 'gauges' in place you can then play with the 'levers,' by implementing Dynamic Voltage and Frequency Scaling (DVFS) schemes or Energy Optimisation Controllers (EOCs) with are able to vary system clock frequencies, supplies and block powering schemes.
Again, we believe that these peripheral monitors are nowadays less 'nice to have' and becoming a more critical requirement. With that, these monitors must be reliable and testable in situ as failing sensors could have a dramatic effect to the system.
Another point is that we're seeing device architectures that cannot cope with each and every block being enabled. With increased gate densities on 28nm bulk and FinFET, hence greater power densities, hence greater thermal dissipation, we're seeing that devices cannot be fully power-up and at the same time, operate within reasonable power consumption limits.
All these problems of coping with PVT conditions on-chip and the increasing process variability on advanced nodes mean that the challenges, and opportunities of innovation, for implementing more accurate, better distributed embedded sensors and effective Energy Optimisation (EO) schemes are here to stay.