I was delighted to receive a significant amount of enthusiastic feedback regarding my talk. The general premise of my talk is seemingly obvious to those of you in this SoC Design Community, but not necessarily to many in the lithography community: The papers at the lithography conferences focus on what line and space can be printed, but when you put an SoC together, there's a lot of other stuff going on.
That other stuff was quite interesting to much of the audience.
Below is a summary write-up of my talk that I'm working on for the SPIE newsroom.
EUV and SoC: Does it Really Help?
Of course EUV, should it meet its production targets, would help. But as we get closer to an actual EUV insertion point, it is informative to move beyond the basic metrics of pitch and wafers per hour to consider the key SoC metrics: Power, Performance, Area, and Cost (PPAC), and how lithography mixes with other concerns to produce the final results. In so doing, we find pluses and minuses that might nudge the argument one way or the other. The first section of my talk detailed that we are in an era where transistor performance is not helped by shrinking the gate pitch. This is primarily due to parasitic resistance and capacitance. This is not solved by switching to a high mobility channel material in the fin or to even a nanowire, but only mitigated. Contacting ever-shrinking transistor source/drains is becoming as limiting of a problem as the transistor itself. Along these lines, I showed cases where larger gate pitch can result in smaller chips. One of the morals of those examples is that the overall chip area is a combination of transistor characteristics and wiring capabilities and the two should be considered together when defining a process technology. A related issue is the scaling of minimum area metal shapes, which are now often not lithographically limited but limited by copper fill. Larger minimum area metal shapes take up more routing resources and can result in larger chips.
Furthermore, the interconnect parasitics that the transistors must drive in order to operate a full circuit are also not helped by feature size scaling. As circuits are scaled, the ratio of wire load to transistor drive can be expected to worsen, and then in order to hit frequency scaling targets the transistor drive strengths have to be increased—either by increasing the width of a given transistor or by increasing the number of repeater gates in a critical path. Either way, area and power suffer due to poor interconnect scaling.
A further aspect challenged by feature size scaling is variability.
Designers must include margins for variability—if we are presented with larger variability, design margins increase, and those larger margins translate into larger, more power-hungry chips. Part of what we are fighting is Pelgrom’s Law, which reminds us that transistor variability increases as we decrease the area of the channel. The fabs have made remarkable progress in reducing this variability over the generations, including a big step with the 2nd generation of FinFETs by including multiple gate work function materials that allow us to reduce the doping in a wider range of transistor options. Historically, the two largest contributors to random variability in transistors have been the dopant fluctuations (reduced as noted above) and line edge roughness (LER) of the gate. With the reduction of the dopant component of random fluctuations, and with FinFETs adding fin edge roughness variability to gate etch roughness, reducing LER in general will become more important. This will be a key issue to monitor with the development of the EUV ecosystem, assource power and resist improvements will be needed to improve LER.
The circuits that are most affected by local variability are the memories. Scaling the minimum area SRAM bitcells (which are typically the ones bandied about in public marketing materials) from 28 to 20 to 16/14 to 10 can take them from relatively normal operation to non-functionality. This does not mean that we can’t make embedded memory anymore, just that designers need to choose one of three actions: Use a bitcell that has larger transistors, use a bitcell that contains more transistors (8 transistors instead of 6 is a popular option) , or wrap “assist” circuitry around the memory arrays which help them overcome their native variability limitations. Any of these options will add area and/or power, and might end up limiting the speed of the chip as well. I received a lot of feedback on this point—underscoring that many people outside of the direct chip design ecosystem did not know that we were already in a regime where the inherent variability of the transistors has limited our abilities to scale memory to the degree that pitch scaling would imply.
The key message of this opening part of the talk: There are many issues that will dilute the final product metrics, independent of the pitch scaling we enable. The good news side of this is somewhat tongue-in-cheek: All of the semiconductor industry isn’t hanging on the fate of EUV pitch scaling.
Transistors, their contacts, and the vias and wires, will all need to have fundamental improvements in order to fully take advantage of the pitch scaling that EUV may offer.
Transitioning to more specific lithography topics, I spent some time comparing the “with-EUV” option to the “without EUV” option (multiple patterning).
In the case of the most critical logic layer, the 1st metal layer, which necessarily contains a high degree of 2-dimensional shapes, we’ve taken on Litho-Etch-Litho-Etch style patterning, making do with this in the absence of EUV. Interestingly, with the great capabilities in overlay in the state-of-the-art 193i steppers, many of our critical 2-dimensional shapes (such as a line end facing the side of a line) may not scale if switched to EUV at a next node, due to the numerical aperture limitations. This disadvantage must be added to the obvious advantage of printing with fewer masks. One wild card here would be the ability to route in M1 with EUV. We removed the ability for the routers to manipulate M1 shapes several technology nodes ago, because the associated rules had become too complex for routers in the extreme low-k1 regimes.
EUV should help with some of the key constructs used to create low power (i.e., small) standard cell logic. A key area is in the local interconnect that is used to wire transistors under the M1. This leads to an interesting point, quantified in a later paper by Lars Liebmann of IBM, that low power designs will likely benefit more from EUV than higher performance designs, as the higher performance designs can use larger standard cells that would not put as much pressure on local patterning.
Another possibility to consider ties back to the interconnect parasitics that I discussed as key scaling limiters above. The only reason we haveadded the local interconnect is to make up for patterning limitations of 193i in these small standard cells.
It’s possible that EUV may allow us to eliminate or at least simplify the local interconnect, saving wafer cost but perhaps also importantly reducing wiring parasitics—which would reduce the area and power of chip implementations, all other things being equal.
There are many other “second order” issues that EUV may help with—meaning chip design issues that extend beyond basic pitch scaling. One example I used was the need for multiple patterning in the signal routing layers. If for instance LELE type multiple patterning is used, different wires on the same metal layer will move with respect to each other, due to misalignment between the different masks of the decomposed layout. This misalignment creates extra capacitance variation, which then increases the required design margins, and as discussed earlier will end up with larger, more-power hungry designs. Self-Aligned Double Patterning (SADP) is a possible alternative to LELE, and with SADP the line spacing won’t vary according to mask overlay, but it will vary according to “pitch walking” due to mandrel CD variation. Furthermore, most embodiments of SADP impose extra restrictions on the placement of line ends (where we via up/down to other metal layers), and any extra restrictions increase chip area. This brings up a point I emphasized during the talk: Many designs, especially low power designs, are limited by the wiring, and much of the wiring limitations are not from simple line/space but from the line ends and the rules associated with vias at the line ends.
Either way we choose to do multiple patterning, we will limit the ability to scale power, performance and/or area (PPA) of our designs, and this is another issue that should be comprehended when comparing EUV to non-EUV options.
Another potential EUV benefit relates to the routers that I mentioned earlier: merely enabling simpler design rules for the routers can result in improved design implementations, because optimizing the PPA of a design typically involves dozens and dozens of iterations of the floor-planning, placing, and routing of the design. The slower the router (due to more complex design rules), the fewer iterations will be possible prior to design tape-out, and the products taping out won’t be able to achieve ultimate PPA entitlement.
And that brings me to the message I wanted to leave the SPIE EUV conference attendees with:
No one would dispute the benefit that an ideal EUV capability would bring to the industry.
But as EUV closes in on its pitch and throughput targets and approaches viability, we must consider the practical design aspects in order to accurately quantify the potential benefit of EUV. Unfortunately, these design questions are not easy to answer—they ideally require a full Process Design Kit (PDK), with transistor models, parasitic extraction models, and wiring design rules, and fully considered implementations of mock designs in order to benchmark the PPA results.
Furthermore, there won’t be one right answer—low power and high performance designs will likely arrive at different value assessments for EUV, which will add complexity to the choices the foundries will have to make regarding the timing and specific process layers for EUV insertion.