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SoC Implementation

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SAN FRANCISCO--Design Automation Conference 2014, more than ever, was about SoC design challenges and solutions, IoT, automotive, embedded market opportunities and how they electronics ecosystem is joining to push ahead into advanced nodes.

If you missed DAC 2014 (and even if you were there and couldn't shape-shift to follow multiple events in parallel) here are some highlights:


I was exhausted at the end of that week and now I know why! My editorial colleagues Schirrmeister, Richard Goering, Sarah Adams, Lani Wong, Christine Young and Sean O'Kane executed a full-court press on DAC to make sure we covered all the bases. Kudos to them and to the team at the ARM Connected Community Brad Nemire, Lori Kate Smith, Leah Schuth,Alban Rampon and all the other ARM CC rock stars!

Related stories:

Everything DAC

DAC 2014 – Five Mega Trends for System Design and Verification

So, that was DAC 2014

DAC Breakfast: 14nm is Real and Ready for Use

The Aftermath of the ARM Step Challenge at DAC

Here's a summary by IEEE's Spectrum Magazine regarding IBM's recent "7nm and beyond" research funding committment:



This is potentially great news for our industry, because IBM has a rich pipeline of research heading toward the post-CMOS nanoelectronics world, and they fill a key niche between University tinkering and foundry manufacturing.  There's a lot more going on at IBM than the couple of snippets provided in this article, so I'm excited to see the news.


And in case you weren't aware, our R&D group here at ARM has a history of working with IBM in the future technology arena:







When it comes to Internet of Things systems, the name of the game is low power and small footprint.


This is often easier said than done in an environment in which designers must take those two huge issues into consideration while figuring out how to implement and verify low-power mixed-signal blocks into cost-effective SoCs and get to market before their competitors.

ARM and Cadence are hosting a webinar July 22 to explore just that: How teams can address Internet of Things (IoT) and (SoC) design and verification challenges in a timely and effective manner.

The webinar will focus on SoC implementation and verification using an ARM Cortex-M0 processor. The Cortex-M0 is ARM’s smallest 32-bit core, consuming as little as 16µW/MHz (90LP process, minimal configuration) in an area of under 12,000 gates.

This turns out to be especially useful for engineers migrating from 8- and 16-bit systems who are keeping their eye on efficient code use but want the performance enhancements that come with a 32-bit architecture.

Diya Soubra, CPU Product Manager for ARM Cortex-M3 processors at ARM, and Ian Dennison, Solutions Marketing Senior Group Director for the Custom IC and PCB Groups at Cadence, will guide listeners through ways to reduce time to market and realize power-performance-area design targets.


Click here to register.


Brian Fuller


Related stories:

--Webinar: Addressing MCU Mixed-Signal Design Challenges

Integration challenges for Connectivity IP in the IoT space – Sunrise Micro Devices is addressing each one of them


I am going to broadly divide IP into RF/Analog IP and Digital IP. Both have unique integration and delivery challenges. Increasingly though, more of the IP is mixed signal. Take us, Sunrise Micro Devices (SMD), for instance. SMD is in the Internet of Things (IoT) market where we expect billions of devices to be connected to the internet in the next few years. Every semiconductor IC device, in addition to having a microprocessor and sensor solution, will need a connectivity solution. IPs in this space are necessarily mixed signal; consequently, they inherit the complexities and issues of both digital and RF IPs.

At a very high level, the main issue with IP is that the simulated environment is different from the final design environment. Analog and RF IP is dependent on process/node, foundry, layout, extraction, model fidelity, and placement. So you are either tied to just dropping it in ‘as is’ and treating it like a black box (nobody knows how it works and whether it meets the required specifications) or completely changing it (with the caveat that you can no longer expect the same results). Digital IP needs to be resynthesized followed by placement and routing, and it takes several iterations to make the IP you got work the way you want it to work. In addition, this process is extremely tool-dependent.


Finally, there are system level issues like interoperability, interface and controls (how does the IP talk to the rest of the SoC). A very important, often overlooked factor is the communication between the IP providers and the SoC implementation houses – there are documents outlining integration guidelines, but without an automated process that takes in all that information, a lot could be lost in translation.


IP is no longer just IP blocks, we now have IP sub-systems. This is very true in our space (IoT market), where a radio solution needs a transceiver, a baseband and a link layer controller – including blocks in RF, Analog, purely digital and mixed signal domains. The only way to address this effectively is to do so at the architectural level. We are seeing fragmented solutions from IP providers, some providing just the transceiver, and some baseband/controller solutions and making integration very difficult.

Very few companies have expertise in both the RF/Analog and digital domains; SMD is an expert in low-power radio design and our Technologist-in-Residence, David Flynn is an ARM Fellow who has extensive experience in the low power digital domain. Together, we have architected a solution to address the problem we see in this IP market. The resulting solution is a Hard Macro (pre-qualified) that has integrated transceiver, baseband and the Link Layer controller. Our radio IP has a peripheral interconnect which is a standard AHB interface that is compatible with most microprocessor architectures, greatly simplifying SoC integration.


Another aspect of system integration is SW availability – We provide firmware required for the radio in the ROM and also provide provision for updates through patch RAM. This along with the timing-independent interface to the host controller in all our IP offerings enables easy implementation of the stack and application layers. We have also paid special attention to system level reset, timing and control


Besides addressing the ‘Ease of integration’ issue at a system and architectural level, we support it via integration and implementation manuals, reference schematics, data sheets and applications notes on antenna selection, PCB layout, Bluetooth qualification, regulatory certifications and production test guidance which enables silicon partners with little or no prior RF experience to bring to market BLE enabled SOCs in a timely, risk-free, and cost effective manner.


Companies/engineers can only can keep up with the explosive growth in computing needs in the market by efficient IP re-use, so I actually see this as a huge potential for third-party IP vendors. There are known issues and IP companies recognize them. Every IP vendor, can address the specific IP integration issues in their domain, differentiate their offerings and offer better solutions. The cream will rise to the top. The vendors that offer effective solutions and ease integration pain points are the ones that will thrive.

Smart and Connected

中文版本 Chinese Version



June 24, 2014, Huawei Technologies officially announced their new smart phone Huawei Honor 6 smartphone in Beijing China, the device uses Hisilicon's new Hisilicon Kirin 920 SoC mobile processor.


For those who donot know Huawei mobile well, Huawei mobile terminals have two ranges, they are Huawei Ascend and Huawei Honor. The difference is that Huawei Ascend mainly targets high-end market, which are divided into four series: D (diamond), P (platinum), G (gold), Y (Young) [check out my blog in 2013 at Huawei Asecond P6 launch event in London Showcasing Huawei's Ascend P6 in ARM Powered Rubik's Cube Solver]. Whereas, Huawei Honor series aim at the mass market, cost-effective, high-profile, major expansion within the Chinese market, particularly wanting to be driven by a young, motivated group, & associate with daily living affordable brand.


The new release of Huawei Honour 6 smartphone uses the latest Hisilicon 8 Core Kirin920 SoC, 28nm HPM, with ARM big.LITTLE CPU -- a Quad-core Cortex-A15 + Quad-core Cortex-A7 processor, eight-core can be opened simultaneously. In other words, it is high-performance with ARM Cortex-A15 processor, low-power with ARM Cortex-A7 processor effect; it also comes with ARM Mali-T628 graphics processor (GPU) [check out ARM CC blog Huawei Chooses ARM Mali GPUs for its Premium Smartphone Offering] and features 3GB of RAM. The Huawei Honor 6 smartphone also features a 5 megapixel front facing camera and a 13 megapixel rear camera, the handset comes with Android 4.4.2 Kit Kat, plus the company’s EMUI 2.3 user interface. The device has an aluminum casing and it also comes with CAT 6 LTE, which supports download speeds of up to 300 Mbps. Although there are different price speculation before the launch, the final announced retail price for the Huawei Honor 6 16GB version is RMB1999 (US$320), 32GB version is RMB2,299 (US$370). This new smart handset will officially be on market from 1 July 2014. Here are some photos from the launch event.



Hisilicon CTO Mr. Wei Ai & President of Huawei Honor Division Mr. Jiangfeng Liu introduced Hisilicon R&D history and Kirin 920 performance, which is eight-core heterogeneous multi-processors (ARM big.LITTLE), five-mode full-band LTE Cat6 300M Modem, also comes with ARM Mali-T628 MP4 GPU based. Hisilicon Kirin920 is now officially launched!


Hisilicon Kirin 920 SoC architecture & performance

photo 2.JPGphoto 4.JPGphoto 5.JPG

Huawei Hornor 6 smartphone retail pricing and onsite products demo area






Here you can find out more about ARM big.LITTLE:


ARM Official Site on big.LITTLE (English, 中文)

ARM big.LITTE micro site - register for relevant news update, download white paper

Ten Things to Know About big.LITTLE

big.LITTLE in 64-bit

What is the latest progress on big.LITTLE technology?

big.LITTLE technology moves towards fully heterogeneous Global Task Scheduling - Techcon Presentation

ARM's big.LITTLE architecture aims to satisfy the hunger for power - Q&A with John Goodacre, Director, Technology and Systems, ARM Processor Division

Power Management with big.LITTLE: A technical overview

big.LITTLE and AMBA 4 ACE keep your cache warm and avoid flushes

Extended System Coherency - Part 1 - Cache Coherency Fundamentals

Extended System Coherency - Part 2 - Implementation, big.LITTLE, GPU Compute and Enterprise

First tape-out with TSMC’s 16nm FinFET and ARM’s 64-bit big.LITTLE Processors

ARM CoreLink 500 System IP — Enabling 64-bit big.LITTLE

ARM & Linaro - big.LITTLE FAQ on Google+ Hangouts


Video on Youtube via ARMflix

ARM big.LITTLE Technology Explained , published on 8 April 2014

Programming for Multicore & ARM big.LITTLE technology (GDC 2014), published on 21 March 2014

ARM® big.LITTLE™ Processing with ARM® Mali GPUs Demonstrating GPU Compute, published on 11 September 2013

ARM® big.LITTLE™ Processing with QuickOffice, published on 10 September 2013

ARM® big.LITTLE™ Processing with Angry Birds game, published on 10 September 2013

ARM big.LITTLE Hangout with the Experts, published on 14 August 2013

ARM big.LITTLE Overview and demonstration, published on 26 October 2012

ARM® big.LITTLE™ Technology, published on 25 October 2012

ARM & Linaro - big.LITTLE FAQ, published on 18 October 2012

ARM Cortex-A7 launch -- big.LITTLE demonstration, Nandan Nayampally, Director, Product Marketing, published on 19 October 2011

Last week, I received the call for papers for the Embedded World Conference for 2015. The list of topics is a good reminder of how broad the world of embedded systems is. It also reminded me how overloaded the term “embedded" has become. The term may invoke thoughts of a system made for a specific purpose to perform a dedicated function, or visions of invisible processors and software hidden in a product like a car. When I think of embedded, I tend think about the combination of hardware and software and learning how they work together, and the challenge of building and debugging a system running software that interacts with hardware. Some people call this hardware dependent software, firmware, or device drivers. Whatever it is called, it’s always a challenge to construct and debug both hardware and software and find out what the problems are. One of the great things about working at Carbon is the variety of the latest ARM IP combined with a spectrum of different types of software. We commonly work with software ranging from small bare-metal C programs to Linux running on multiple ARM cores. We also work with a mix of cycle accurate models and abstract models.


If you are interested in this area I would encourage you learn as much as possible about the topics below. Amazingly, the most popular programming language is still C, and being able to read assembly language also helps.

  • Cross Compilers and Debuggers
  • CPU Register Set
  • Instruction Pipeline
  • Cache
  • Interrupts and Interrupt Handlers
  • Timers
  • Co-Processors
  • Bus Protocols
  • Performance Monitors

I could write articles about how project X at company Y used Carbon products to optimize system performance or shrink time to market and lived happy ever after, but I prefer to write about what users can learn from virtual prototypes. Finding out new things via hands-on experience is the exciting part of what embedded systems are for me.

Today, I will provide two examples of what working with embedded systems is all about. The first demonstrates why embedded systems programming is different from general purpose C programming because working with hardware requires paying attention to extended details. The second example relates to a question many people at Carbon are frequently asked, “Why are accurate models important?” Carbon has become the standard for simulation with accurate models of ARM IP, but it’s not always easy to see why or when the additional accuracy makes a difference, especially for software development. Since some software development tasks can be done with abstract models, I will share a situation where accuracy makes a difference. Both of the examples in this article looked perfectly fine on the surface, but didn’t actually work.

GIC-400 Programming Example

Recently, I was working with some software that had been used on an ARM Cortex-A9 system. I ported it to a Cortex-A15 system, and was working on running it on a new system that used the GIC-400 instead of the internal GIC of the A15.

People that have worked with me know I have two rules for system debugging:

  1. Nothing ever works the first time
  2. When things don’t work, guessing is not allowed

When I ran the new system with the external GIC-400, the software failed to start up correctly. One of the challenges in debugging such problems is that the software jumps off to bad places after things don’t work and there is little or no trail of when the software went off the path. Normally, I try to use software breakpoints to close in on the problem. Another technique is to use the Carbon Analyzer to trace bus transactions and software execution to spot a wrong turn. In this particular case I was able to spot an abort and I traced it to a normal looking access to one of the GIC-400 registers.

I was able to find the instruction that was causing the abort. The challenge was that it looked perfectly fine. It was a read of the GIC Distributor Control Register to see if the GIC is enabled. It’s one of the easiest things that could be done, and would be expected to work fine as long as the GIC is present in the system. Here is the source code:


The load instruction which was aborting was the second one in the function, the LDRB:


The puzzling thing was that the instruction looked fine and I was certain I ran this function on other systems containing the Cortex-A9 and Cortex-A15 internal GIC.


After some pondering, I recalled reading that the GIC-400 had some restrictions on access size for specific registers. Sure enough, the aborting instruction was a load byte. It’s not easy to find a clear statement specifying a byte access to this register is bad, but I'm sure it's in the documentation somewhere. I decided it was easier to just re-code the function to create a word access and try again.


There are probably many ways change the code to avoid the byte read, but I tried the function this way since the enable bit is the only bit used in the register:


Sure enough, the compiler now generated a load word instruction and it worked as expected.


This example demonstrates a few principles of embedded systems. The first is the ability to understand ARM assembly language is a big help in debugging, especially tracing loads and stores to hardware such as the GIC-400. Another is that the code a C compiler generates sometimes matters. Most of the time when using C there is no need to look at the generated code, but in this case there is a connection between the C code and how the hardware responds to the generated instructions. Understanding how to modify the C code to generate different instructions was needed to solve the problem.


Mysterious Interrupt Handler


The next example demonstrates another situation where details matter. This was a bare-metal software program installing an interrupt handler for the Cortex-A15 processor for the nIRQ interrupt by putting a jump to the address of the handler at address 0x18. This occurs during program startup by writing an instruction into memory which will jump to the C function (irq_handler) to handle the interrupt. The important code looked like this, VECTOR_BASE is 0:


The code looked perfectly fine and worked when simulated with abstract models, but didn’t work as expected when run on a cycle accurate simulation. Initially, it was very hard to tell why. The simulation would appear to just hang and when the simulation was stopped and it was sitting in weird places that didn’t seem like code that should have been running. Using the instruction and transaction traces it looked like an interrupt was occurring, but the program didn’t go to the interrupt handler as expected. To debug, I first placed a hardware breakpoint on a change on the interrupt signal, then I placed a software breakpoint on address 0x18 so the simulation would stop when the first interrupt occurred. The expected instruction was there, but when I single stepped to the next instruction the PC just advanced one word to address 0x1c, and no jump. Subsequent step commands just incremented the PC. In this case there was no code at any other address except 0x18 so the CPU was executing instructions that were all 0.


This problem was pretty mysterious considering the debugger showed the proper instruction at the right place, but it was as if it wasn’t there at all. Finally, it hit me that the only possible explanation was that the instruction really wasn’t there.


What if the cache line containing address 0x18 was already in the instruction cache when the jump instruction was written by the above code? When the interrupt occurred the PC jumps to 0x18 but would get the value from the instruction cache and never see the new value that had been written.


The solution was to invalidate the cache line after writing the instruction to memory using a system control register instruction with 0x18 in r0:


Although cache details are mostly handled automatically by hardware and cache modelling is not always required for software development, this example shows that sometimes more detailed models are required to fully test software. In hindsight experienced engineers would recognize self-modifying code, and the need to pay attention to caching, but it does demonstrate a situation where using detailed models does matter.




Although you may never encounter the exact problems described here, they demonstrate typical challenges embedded systems engineers face, and remind us to keep watch for hardware details. These examples also point out another key principle of embedded software, old code lives forever. This often means that while code may have worked on one system, it won’t automatically work on a new system, even if they seem similar. If these examples sound familiar, it might be time to look into virtual prototypes for your embedded software development.


Jason Andrews

AppliedMicro is hosting a panel discussion with keynotes from HP and Sandia on HPC workloads using AppliedMicro’s X-Gene SoC that is based on ARM 64-bit architecture at ISC’2014 this week. Following the keynotes, a partner panel will feature ARM, Boston, E4 Computer Engineering, Eurotech, Mellanox and NVIDIA. ARM’s Andrew N. Sloss, Senior Principle Engineer, will be speaking during the panel session on June 24, between 1:00 – 2:00 p.m. CEST, at Congress Center Leipzig, Germany, in Room M02. For more information on the panel, contact jbrendel@apm.com or tliew@apm.com. To see live demonstrations of X-Gene in HPC, visit the AppliedMicro booth (#506) at ISC 2014.


For more information on AppliedMicro’s X-Gene, read today’s announcement, AppliedMicro Announces Readiness of 64-bit ARM®-based Server SoC for High Performance Computing.

SAN FRANCISCO--We've written a lot about the really fun, really clever ARM Step Challenge at DAC 2014. From the initial The ARM Step Challenge at DAC: Throwing Down the Gauntlet post to The Aftermath of the ARM Step Challenge at DAC.

Sean O'Kane took me aside on the floor of Moscone Center to do a brief retrospective for ChipEstimate TV. John Heinlein and Phil Dworsky might want to take a look!

Now that DAC's in the rear view mirror, I know I'm joined by all competing partners in looking forward to doing it again at ARM TechCon (Oct. 1-3) in Santa Clara.

Keep on truckin'!


As a huge baseball fan.. I was disappointed that the Giants were not in San Francisco this week.

Then I went to the 51st annual Design Automation Conference and found that ARM was hitting the home run I wanted to see.

The ARM Connected Community was out in force on the exhibition hall.  We showed how complete the solution stack is for developers using ARM IP.

From Design to Verification to Software to Foundry there were great examples of how to pull it all together and get products done.

We had partners like  Phil Dworsky from Synopsys showing their full range of solutions from Galaxy Design Platform support to

FPGA Prototyping solutions and everything in between.


And we had Cadence showing how real IoT solutions get done.



Here is my old friend Valerie Rachko from Mentor Graphics Corporation showing real solutions for Embedded Debug and Questa, one of the industry standard products for functional verification.


What struck me on a day where Intel made some announcements on the beginnings of their EDA partnerships, is how rich our solution truly is..

Companies of all sizes partner with ARM to innovate in Software and Hardware.  I am personally interested in the role that memory technology plays in the future..
I found one demo in the connected community booth really interesting.

For embedded applications (IoT and the like) a company called Memoir Systems has a a tool for automatic generation of a diverse set of memory architectures based on Artisan IP.



So I went to the Intel Booth and what did I find?

I found a fine demonstration of Wind River Simics doing software debug on ARM.  Another example of how complete our story is.


From the time a team thinks about a product to develop to the time its done, there are strong tools for design, development and management of that project.  Tools like the ARM DS-5 Development Studio, or from our many EDA partners, even.. Intel

On the last day of the conference, the ARM VP for PIPD Dipesh Patel gave his visionary keynote.  He said "It has never been easier to develop complex SOC!" ?? Whoa.. and had I not spent the week there. I would have been stunned by this claim.. EASY?

This is EASY?   but when he said it .. I said "yep.. about right".

At the beginning of the year, Cadence introduced a great new video series and blog called Whiteboard Wednesdays. Each Wednesday, our engineers bring you a chalk talk-like series of insights on semiconductor and systems IP design issues we all face today, whether it's Scott Jacobson talking about how to close the memory wall gap in our inaugural Whiteboard Wednesday video or last week's edition in which Arif Khan takes a closer look at PCI Express and its role in improving power optimization:



Here's a selection of popular Whiteboard Wednesdays to date:

Here's a link to our Whiteboard Wednesdays blog with the complete listings, updated each week, and the link to our Cadence YouTube playlist.

GLOBALFOUNDRIES has two upcoming Technical Seminars in China and Taiwan.


Both events include GLOBALFOUNDRIES presentations about device manufacturing collaboration for mainstream and leading edge offerings, as well as an overview of its BCDlite. Senior Executives will provide an overview about GLOBALFOUNDRIES and collaboration strategies for customers and partners located in China and Taiwan, respectively.


ARM will have a tabletop booth at both of these seminars. We will be showing our Artisan products available for GLOBALFOUNDRIES.


The first is their annual China Techncal Seminar in Shanghai on Wednesday, June 25, 2014.

Time: 8:00 am to 5:00 pm

Location: Kerry Hotel

No.1388 Hua Mu Road

Pudong, Shanghai

201204, China

More information on the Shanghai seminar, including registration, can be found here.



Two days later is their annual Taiwan Techncal Seminar in Hsinchu on Friday, June 27, 2014.

Time: 8:00 am to 5:00 pm

Location: Ambassador Hotel

No.188, Sec. 2, Zhonghua Rd




More information on the Taiwan seminar, including registration, can be found here.


Agenda for both locations

8:00 am - 9:15 amRegistration and networking breakfast
9:15 am - 9:20 amOpening Speech and Seminar Introduction
9:20 am - 9:50 amGLOBALFOUNDRIES update & Foundry 2.0
9:50 am - 10:35 amEnabling SoC Innovations from "Sensors to Servers" through advanced technology R&D
10:35 am - 11:00 amTea break
11:00 am - 12:00 pm28 nm in Production at GLOBALFOUNDRIES, are you ready to join?
12:00 pm - 1:00 pmLunch break + Raffle sessions
1:00 pm - 1:45 pmEmbedded NVM Platforms and Applications
1:45 pm - 2:30 pmBCDlite: (analog/power and RF technology solutions, microcontroller, mobile display, secure devices)
2:30 pm - 3:15 pmGLOBALFOUNDRIES RF Technologies
3:15 pm - 3:25 pmTea break
3:25 pm - 4:10 pmMEMS update
4:10 pm - 4:55 pmGLOBALFOUNDRIES 3D and 2.5D Technology Status
4:55 pm - 5:00 pmConclusion of GLOBALFOUNDRIES Technical Seminar




Going to Amsterdam next week?


Taiwan Semiconductor Manufacturing Corp. (TSMC)  is holding their European Technology Symposium in Amsterdam.


  • Date: Tuesday June 17, 2014
  • Time: 8:30am-4:00pm
  • Location: Sheraton Amsterdam Airport Hotel and Conference Center (Schiphol)
    • Schiphol Boulevard 101 
    • Amsterdam,1118BG Netherlands


ARM will have a tabletop booth at this event. We will be showing our the ARM Artisan products available at TSMC.


Registration and more information here.



8:30Registration Opens
9:35 – 9:50Welcome and Remark
9:50 – 10:35Industry Overview and Corporate Updates
10:35 – 10:55Morning Break
10:55 – 11:35Technology Leadership
11:35 – 12:05Manufacturing Excellence
12:05 – 13:00Lunch
13:00 – 14:00Specialty Technology for Analog, High Voltage, MEMS, and Power Management
14:00 – 14:30EFlash Technology for Smart Card, Automotive, & General MCU Segments
14:30 – 15:00Coffee Break
15:00 – 15:30TSMC Technology Platform for Internet of Things
15:30 – 16:00TSMC SiP Platform (Backend Technology)
16:00 – 16:30Social Hour



Mark the date for the 2014 Foundry Technology Symposium hosted by MagnaChip Semiconductor!


Time : 9:00 am ~ 5:00 pm, June 12th (Thursday), 2014

Venue : Hilton Santa Clara, 4949 Great America Pkwy, Santa Clara, CA 95054


Look for presentations on Company Overview & Business Update, Mixed-Signal, BCD/UHV and NVM Technology. In addition, keynote speakers from IHS, Aeroflex and ARM will address “Semiconductor & Foundry Market”, “Using commercial wafer foundries for high-reliability, harsh-environment microcircuit applications” and “The IoT (Internet of Things) and how it is shaping our future”.


We hope you will join the 4th annual tech. symposium!


You can register on the MagmaChip Web site or at ifoundry.magnachip.com


Please see the attached document for the detailed agenda.




Two very different analysts stress the importance of software in chip and server ecosystems.


Last week, veteran semiconductor electronic design automation (eda) analyst garysmith made the following observation about ecosystems in his annual Design Automation Conference (dac_2014) kick-off presentation: “With such a range of possible original equipment manufacturer (OEM) scenarios, you (chip designers) need to understand who is your customer and who is your competitor. And the relationships almost change day by day. The key is to develop an ecosystem as stable as ARM’s in this changing world of relationship.”


Smith’s comments were part of his discussion about the need for a larger system approach to chip design with a complementary need for a strong ecosystem. Both needs were driven by the changing roles of chip design tool vendors within the semiconductor (hardware and software) electronics supply chain. A traditional OEM would buy the platform design, manufacture the system-on-chip (SoC) at a foundry, wrap plastic around it and take it to market (e.g., low end cell phones). However, today’s OEM could also be a vertically integrated company that outsources manufacturing (e.g., high-end Apple cell phones).



Yesterday, Canaccord Genuity issued an equity report in which analyst Matthew Ramsay noted that, “ …the nascent ARM server ecosystem is gaining momentum and the eventual royalty opportunity for ARM will prove larger than consensus expectations, certainly larger than management conservatively has forecast to investors.”


Here, again, was another statement about the importance of ARM’s ecosystem. Taken together, Smith’s and Ramsay’s comments cover a wide portion of the semiconductor market, namely, System-on-Chip (SoC)/IP and cloud-based servers.


What are the common differentiators in each of these markets? Software! Both are industries where hardware is maturing and being commoditized. That’s why it is the software that plays the differentiating role in determining market share, from firmware to applications. To emphasize this point, Ramsay added this comment about ARM’s competitive and technological advantage (over Intel): “Operating system and software support - The role of and increasing momentum behind software/OS support for ARM servers including Linux/Windows and industry groups such as Linaro and ARM’s Server Base System Architecture (SBSA).”


Do you agree? I’d like to get your take on software’s part in this varied ecosystem. - JB

Day 3 of DAC closed with 6 system design related customer and partner presentations at the DAC Cadence Theatre. I also was on Jim Hogan’s Internet of Things (IoT) panel reported on by Paul McLellan and a panel on Automotive System Engineering Methods. This post is really to recap my perspective on the megatrends I saw at DAC 2014, to prove with pictures that EDA is a fun bunch and of course have you join the join the EDA Soccer Pool for the Soccer World Cup starting this Thursday (choose “EDA Soccer” when registering)!


Just like System Design at Day 1 of DAC – Low Power and Ecosystem Key Advantages for ARM and System Design at Day 2 of DAC – Automotive a Key Driver for System Design, Day 3 of DAC 2014 illustrated great examples of partners and customers at the Cadence DAC Theatre – Methods2Business, Kozio, AMD, Broadcom, NVIDIA, DINI, CSR and Bluespec. Details will be posted on our DAC 2014 Theatre Site in due course, but I will include the highlights below. You can also follow our live event blog that we ran during DAC 2014.


Five Mega Trends

In looking back at DAC 2014 last week, five mega trends for system design and verification stick out for me: software everywhere, application verticals, the importance of ecosystems, blurring lines between execution engines and links to new adjacencies. Most importantly though, DAC 2014 was another example on how real users achieve real and quantifiable results using system design.

  1. Software Everywhere: Software is not only driving functionality but is also a key for verification, with one of the promises being to be re-usable across all engines from virtual prototypes through RTL simulation, emulation, FPGA based prototyping and even the actual silicon. Our panel on the Shift to Software Driven Verification with AMD, ARM, Microsoft, Cadence and Vista Ventures emphasized some of the challenges including HW/SW integration and having to anticipate unknown software (ARM), the complexity of chips with 20+ processor cores (Microsoft) and software workloads doubling emulation usage just in the last year (AMD).
  2. Application Verticals: The higher up we move in abstraction, the more application specific the tools become. Verticals that stuck out at DAC were Mobile, Networking and Automotive. On Jim Hogan’s IoT panel we all agreed that verticals will be important to enable the IoT, and a lot of the demonstrations were tailored around them. There were specific inputs from Fiat Chrysler on how software in automotive is driven by regulation, safety and fuel economy, as well as a very inspiring presentation on Chrysler’s turnaround by Klaus Busse, including references to how the software – hardware split is now 85% to 15% in some areas of the car.
  3. Importance of Eco-Systems: Nobody can do it alone. Vendors align around corners-tones in eco systems. TSMC and ARM are corner-stones for chip implementation. In the front-end, ARM is a corner-stone for system design and verification and DAC was a clear demonstration how close Cadence and ARM have become. We had a Cadence demo pod at the ARM booth showing Interconnect Workbench and ARM Fast Models in hybrid mode with emulation, as well as ARM specific demos at the Cadence booth. We had ARM specific demo suite presentations. We also worked closely with ARM on a tutorial called “Optimizing ARM®-Based SoCs for Performance and Speeding System Validation” and ARM presented in our Cadence Theatre on “Accelerating Graphics Software Simulation in Virtual Platforms”. Cadence itself is a corner-stone for an EDA specific ecosystem as well – 8 of the 14 system design related presentations at our theatre were given by partners.
  4. Blurring Lines Between Execution Engines: Cadence has been referring to the System Development Suite since May 2011 in a way that “no engine can do it all”, every engine has advantages and disadvantages. DAC 2014 clearly illustrated how the lines between the different execution engines are blurring – there were hybrids of virtual platforms and emulation (NVIDIA, AMD, CSR), hybrids of virtual platforms and FPGA Based Prototyping, combined use of emulation and FPGA based prototyping (Solarflare), acceleration, i.e. the combination of RTL simulation and emulation. And all of them need to be connected to either virtualized or live system environments, representing the peripherals a chip has to talk to.
  5. Links to New Adjacencies: This is the area in which future improvements will enable a next wave of system design – we are working with some key partners in our eco-system already. Kozio and National Instruments presented how to bring post-silicon validation methods into the pre-silicon phase. Intel Co-Fluent and Methods2Business presented on connecting high-level synthesis to system modeling tools and raising the level of design entry at which one model drives high-level synthesis and virtual prototyping. Other players in our eco-system – Xilinx, Bluespec and DINI – showed how their offerings work together with our FPGA based prototyping system RPP.


Here are some of the real results users reported on using system design approaches. There were many more, but these stuck out to me:

  • CSR achieved up to 200x speed improvement for software development using ARM Fast Models in the Cadence Virtual System Platform together with Cadence Palladium XP.
  • NVIDIA achieved 10x speed –up for the ARMv8 Tegra Hybrid booting Android with a 64b’ Kernel and 32b’ User space, was able to fix interface issues early and used it to demo capabilities to partners. The 10x seems at the low end of what hybrid can do and is partly related to the speed of the ARMv8 Fast Models. As ARM’s Rob Kaye points out in a description of the latest Fast Model release, the just released new v8 models are about 2.5x faster, so NVIDIA can likely expect significant more speedup when switching to the latest.
  • AMD achieved up to 200x speed improvement for their hybrid configuration, was able to verify that correct events and sequencing occurred per architecture spec and determined that their software is correctly controlling power management states.
  • Solarflare showed how they were emulating a dual-port 10G/40G NIC on RPP and Palladium, a great example how using the same flow for bring-up in Palladium and RPP helped them to get to market faster.


All in all, DAC 2014 was great for system design and verification, as shown above. In addition it showed once again how EDA is actually a fun community. As the pictures below prove, even though we compete by day, we know how to party too.


Jim Hogan’s band is an assembly of cross company music lovers with participants from VMware, Cadence, Sonics and more, the picture was taken at a charity event at Slim’s. What a great gig.


The second picture was taken by Angelo from Synopsys at the Denali Party by Cadence on Tuesday night and shows Mathilde at Calypto originally from Paris, France being twirled on the dance floor by me, Frank at Cadence, originally from Berlin, Germany. Obviously EDA knows no country or company borders here when it comes to having fun after a hard day of work!


And last not least – the Soccer World Cup is upon us!!! If you are a soccer fan like me and like to bet, we have created an EDA Soccer Pool. Simply follow the link and choose “EDA Soccer” when registering. Entry fee is $20 Canadian and as I post this on Tuesday night, there are almost 100 participants in the total pool (“EDA Soccer” is a sub-pool), valuing the overall pool at around $2000 Canadian. All entries must be submitted online by June 12, 2014 - 4:00pm EST. And for my friends on that island close to Europe, no, there is no “ABE” you can choose from, you actually have to make specific picks


Enjoy the World Cup! Best, Frank Schirrmeister

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