The new Cortex-A Series Programmer's Guide for ARMv8-A is available now and does not require a click-through agreement to download.
Besides a general introduction to the ARMv8-A architecture, the guide covers:
The most significant change introduced in the ARMv8-A architecture is the addition of a 64-bit instruction set called A64. This set complements the existing 32-bit instruction set architecture. This addition provides access to 64-bit wide integer registers and data operations, and the ability to use 64-bit sized pointers to memory.
The AArch64 execution state provides thirty one 64-bit general-purpose registers.
ARMv8-A also includes the original ARM instruction set, now called A32.
There are now thirty-two 128-bit registers, rather than the 16 available for ARMv7.
Smaller registers are no longer packed into larger registers, but are mapped one-to-one to the lower-order bits of the 128-bit register. A single precision floating-point value uses the lower 32 bits, while double precision value uses the lower 64 bits of the 128-bit register.
ARMv8-A supports both single-precision (32-bit) and double-precision (64-bit) floating-point vector data types and arithmetic as defined by the IEEE 754 floating-point standard.
The ABI specifies fundamental rules to which all executable native code modules must adhere so that they can work correctly together.
In ARMv8-A, execution occurs at one of four Exception levels. In AArch64 state, the Exception level determines the level of privilege, in a similar way to the privilege levels defined in ARMv7.
For many applications, porting code from older versions of the ARM Architecture, or other processor architectures, to A64 means simply recompiling the source code. However, there are a number of areas where code is not fully portable such as constants, atomic load and store, and conditional execution.
The ARMv8-A architecture employs a weakly-ordered model of memory. In general terms, this means that the order of memory accesses is not required to be the same as the program order for load and store operations. Hardware optimizations, such as the use of cache and write buffer, improve the performance of the processor. Bandwidth between the processor and external memory can be reduced and the long latencies associated with such external memory accesses are hidden.
The ARMv8-A architecture provides a significant level of support for systems containing multiple processing elements.
The Cortex-A53 and Cortex-A57 processors support coherency management between the different cores in a cluster to ensure that all processors or bus masters within a system have the same view of shared memory.
Coherency management and a shared interrupt controller simplify creating big.LITTLE systems that combines energy-efficient LITTLE cores with high-performance big cores.
The exception level access restrictions and TrustZone extensions provide high security for multiple processors running at different privilege levels.
Platform models enable development of software without the requirement for actual hardware. Software models provide models of processors and devices from the perspective of a programmer. The functional behavior of a model is equivalent to real hardware.
The programmer's guide complements rather than replaces other ARM documentation for the Cortex-A series processors.
For information on a specific processor, see the appropriate ARM Technical Reference Manual:
The most important and definitive reference for the ARMv8-A architecture remains the ARMv8-A Reference Manual.
Read ARMV8-A Reference Manual