It has been a busy month for ARM in the infrastructure space. ARM TechCon 2014 started it off with ARM silicon, OEM and ecosystem partners demonstrating their new SoCs, hardware and software platforms. The show also had several talks discussing the challenges within infrastructure and the need for innovation. Neil Parris discussed one aspect in his recent blog, Heterogeneous Compute Requirements in Network Infrastructure, where he described how different cores for different tasks are required to optimize Software Defined Networking (SDN) and Network Functions Virtualization (NFV) solutions.
The month then wrapped up at the Linley Processor Conference where Ian Forsyth presented Scalable ARM-Based Solutions from Sensor to Server, from Edge to Core. Ian discussed how the growth of IoT and smart devices are stressing the current system and announced two new members to the CoreLink Cache Coherent Network (CCN) Family to help tackle the challenge, the CoreLink CCN-502 and CoreLink CCN-512.
So where do the new CoreLink CCN interconnects fit?
One common theme throughout the recent shows, blogs and talks - there is a need for more efficient, optimized solutions from edge to core. ARM Cortex A-Series Processors with CoreLink System IP provide a common architecture across the spectrum, scaling from cost efficient home gateways to high performance core networking and server applications. The CoreLink CCN-502 fits between the CoreLink CCI-400 and CoreLink CCN-504, enabling power and cost efficient small to mid-range solutions. The CoreLink CCN-512 increases the compute density by supporting up to 48 cores.
CoreLink CCN-512 – Maximize Heterogeneous Compute
On the high end of the performance spectrum, macro base station and cloud applications require dense, efficient compute platforms with the right-sized cores to match the appropriate workload. High performance cores are required for server compute and control plane processing, efficient small cores are required to maximize packet throughput and customized accelerators are needed for Layer-1, security and content delivery processing.
With up to 12 CPU Clusters (48 cores), 4 channels of DDR4-3200 memory, and 32MB of Level 3 System Cache, the CoreLink CCN-512 is well suited to maximize heterogeneous processing on a single SoC while maintaining bandwidth up to 1.8 Tb/s.
CoreLink CCN-502 – High Performance, Small Footprint
On the low power and cost efficient end, there is a need to deploy many smaller devices to fill gaps or connect devices on a budget. If you look closely around office buildings or shopping malls, you’ll see cellular repeaters, small cell base stations, and WiFi access points scattered throughout to ensure our smart devices are always on, always available.
With up to 4 CPU clusters (16 cores) and optional Level 3 System Cache, the area optimized CoreLink CCN-502 is the ideal interconnect for these small systems that still demand performance. It is up to 70% smaller than the CoreLink CCN-504 (at the 1MB L3 System Cache design point), yet still capable of maintaining bandwidth up to 0.8Tb/s.
With CoreLink CCN-504 SoCs already in production, the new family members build upon a proven architecture and offer the same enterprise class features; native AMBA 5 CHI interfaces for high frequency, non-blocking data transfers, end-to-end QoS (Quality of Service) and RAS with CoreLink DMC-520, and extensive clock gating and retention states for optimal power efficiency.
In summary, the CoreLink Cache Coherent Network Family provides a common platform for ARM silicon providers to customize scalable systems from edge to core; platforms with a common software framework across heterogeneous systems to meet diverse price, performance and environment requirements.
For more information on the CoreLink CCN Family, please visit the CoreLink Interconnect Homepage - CoreLink Interconnect - AMBA on-chip connectivity - ARM.