Are you a designer who is too busy to attend ARM TechCon in Santa Clara later this week? Then think again, you might well save a lot more time than the day spent to attend. You’ll get the chance to learn about and see the demo of the latest and truly greatest tools for automating IP design. We are previewing a new Socrates design environment recently acquired with ARM’s purchase of Duolog Technologies on theARM booth 300.
What I want to highlight in this blog is how ARM has used the versatile Socrates platform to create a tool that has the effect of combining years of engineering experience in an easy-to-use tool. That’s literally decades of experience encapsulated in hundreds of rules and algorithms of what to do and what not to do when creating either a CoreSight debug and trace system or a CoreLink interconnect system.
System IP configurability is a key aspect to designing the very best SoCs, but with it comes increased complexity of design choices, system integration and verification. System IP configurability has evolved from simple hardware parameterization to highly configurable architectures and IP boundaries. We will look at how configurability is modeled in design flows and try and understand where current design flows are limited.
A defining feature of any system interconnect or debug and trace solution is its configurability, which I touched upon in my last blog. This configurability is vital for its function and makes it versatile for specific user requirements. The simple fact is that no two SoCs are the same, and the sytem IP needs to adapt to match. However, it often raises a number of design decisions.
You begin to ask yourself:
“Do I need this feature?
What is the best value to set this parameter to?
How do I pick the most appropriate option for my SoC?”
These questions can often mount up, along with the nagging doubt that "Maybe I haven’t configured all my components to fit together correctly. I really don’t want a deadlock situation." Much like tuning a Formula 1 car engine, there are so many variables that can be tweaked that it can be difficult to settle on a setup that maximises the performance for a specific use while making sure that there is balance across the system.
What ARM has done with the Socrates design environment is create a tool that instantiates all of these connections through the use of rules and algorithms, thus ensuring that your system is correct-by-construction and unleashes the full potential of your CoreLink or CoreSight IP. In essence, it combines the intelligence and experience of our tech leads, system architects and support engineers inside one toolbox that allows you to package interfaces, build micro architectures and test connectivity in an easy-to-use design
environment. This allows you to cut through the noise of all the connection options and choose the one that works best for you. At ARM TechCon we are previewing two tools with this built in intelligence to take your design intent, the high level spec of what you need the CoreLink or CoreSight system to do. It then automates the configuration and connection of all the necessary IP blocks to create the required sub-system and verify its correctness, give estimates of its area & performance and generate all the output you need to take the design forward into the implementation stage. The new design environment delivers productivity in two main ways:
- It automates the mechanical and repetitive tasks for you, cutting out the risk of errors
- It assists you in the real design choices only the designer can make
Some mechanical aspects are ripe for automation and save months of error-prone donkey work: identifying the exact interface definitions you need to connect to via IP-XACT descriptions and matching your system interface to them, generating precise and easily sharable documentation of your design; generating testbenches and test codes around your system, to name but three. Of course there are some design tasks that are more subtle and require a combination of intelligent algorithms along with the designer’s input in order to create a system that fits the user requirements. This mixture of necessary functions and new features is how architects can really differentiate their SoCs and add value to customers. Here instant feedback on the area and performance of the design guides those design trade-off decisions, leading to the most appropriate design. And anything you have modified manually still gets the automatic checking. This all adds up to a more optimised SoC that is designed faster and with less risk.
So to all those overworked engineers, I hope after reading this you’ll make the time to learn how to save a lot of time and come and visit us on booth #300 this Wednesday or Thursday or catch Simon Rance's technical session Friday 3:30pm.