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ARM Processors

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One of the topics that is of growing interest is to use a hypervisor on an applications processor alongside a TrustZone based TEE.   This new white paper from Mentor give a great introduction to the topic.



I would add that the growing popularity of ARM Trusted Firmware

ARM-software/arm-trusted-firmware · GitHub

makes the integration of these systems much easier than it used to be.  On ARMv8-A (64/32-bit architecture) based platforms we have a new exception level (EL3) which is typically used for Trusted Boot and a small run-time doing the world switch, PSCI, interrupt routing etc.   ARM Trusted Firmware provides a reference implementation for this EL3 code and has been ported to many platforms including our own Juno development board.





Let's be honest, debug can be a bit of a pain. At the best of times it's a nuisance and in the worst case scenario a complex web of wires that need to be configured properly in order to diagnose and solve your SoC design problems. A study conducted by Cambridge University found that the global cost of debugging was $312bn in 2013, a figure that undoubtedly has risen in the past two years. With this much money and effort dedicated to this part of SoC design, it is necessary to be as efficient as possible when debugging. CoreSight technology from ARM provides solutions for Debug and Trace of complex SoC designs. It can take years to become an expert in the finer details of CoreSight, but in this series of blogs I intend to provide readers with a starting point to understand the concepts which will help you to work with CoreSight. Like any good technical introduction, let's start with some definitions



Debug: This refers to features to observe or modify the state of parts of the design. Features used for debug include the ability to read and modify register values of processors and peripherals. Debug also includes the use of complex triggering and monitoring resources. Debug frequently involves halting execution once a failure has been observed, and collecting state information retrospectively to investigate the problem.


Trace: CoreSight provides features which allow for continuous collection of system information for later off-line analysis. Execution trace generation macrocells exist for use with processors, software can be instrumented with dedicated trace generation, and some peripherals can generate performance monitoring trace streams.

Trace and Debug are used together at all stages in the design flow from initial platform bring-up, through software development and optimization, and even to in-field debug or failure analysis.

Historically, the following methods of debugging an ARM processor based SoC exist:



Conventional JTAG debug (‘external’ debug)

This is invasive debug with the processor halted using:

• Breakpoints and watchpoints to halt the processor on specific activity.

• A debug connection to examine and modify registers and memory, and provide single step execution.


Conventional monitor debug (‘self-hosted’ debug)

This is invasive debug with the processor running using a debug monitor that resides in memory.



This is non-invasive debug with the processor running at full speed using:

• A collection of information on instruction execution and data transfers.

• Delivery off-chip in real-time, or capture in on-chip memory.

• Tools to merge data with source code on a development workstation for future analysis.



CoreSight technology addresses the requirement for a multi-processor debug and trace solution with high bandwidth for entire systems beyond the processor, despite ever increasing SoC complexity and clock speeds. Efficient use of pins made available for debug is crucial.


CoreSight provides:

  • A library of modular components and interconnects.
  • Architected discovery and identification methods to allow for flexible system design and easy inclusion of differentiated debug/trace functions.
  • A standard implementation of the ARM Debug Interface for debug tools to work with.




Elements of a CoreSight design


The CoreSight architecture introduces a number of key concepts which together enable complex systems to be designed. Standardized programming models and feature discovery registers allow debug tools to be largely generic with minimal dependence on the feature set of an individual SoC.



Debug Access Port

The Debug Access Port (DAP) is present on any SoC which presents a physical port to be connected to external debug tools. The DAP is an implementation of the standardized ARM Debug Interface, and provides a bridge between a reliable low pin count interface and on-chip memory mapped peripherals. Check out my next blog for more details on the DAP. Transactions generated by the DAP are referred to as External Debugger Accesses.

The DAP provides (amongst other things) architected top level control for debug domain power control, and fast code download direct to system memory.

CoreSight components implement memory mapped interfaces, but the DAP can also act as a bridge to an on-chip JTAG scan chain where necessary for legacy components. This gives increased flexibility and power savings when working with multiple clock and power domains on the SoC.



Self Hosted Debug

Most processors have direct access to their own debug resources by using dedicated instructions. In addition, it is common for most processors on a SoC to have access to some or all of the remaining debug components. Exact details vary, but there is typically a region in the system memory map which is multiplexed with external accesses to the debug components. Self hosted debug is typically managed by debug monitor software running on either the target processor or a second processor in the SoC. Access control mechanisms are provided to permit interworking between an external debugger and self-hosted debug such that the external debugger does not need to be aware of the actions of the debug monitor.

Save and Restore sequences can be used by on-chip software to maintain the debug state across power-down cycles, and provide the illusion to the external debugger that the SoC remains powered on. This is particularly important for debug of battery powered devices where infrequent events are being monitored.



Discovery using ROM Tables

All CoreSight systems will include at least one ROM table. This serves the purpose of both uniquely identifying the SoC to an external debugger, and allowing discovery of all of the debug components in a system. Discovery relies on the use of identification registers at architected positions in the memory map of every debug component. All CoreSight components use this standard. This permits discovery sequences of identify at least a sub-set of the feature-set without detailed knowledge of every component. For both external debug, and self-hosted debug, there is a pointer to the address of the top-level ROM table from that debug agent. The ROM table provides a list of address offsets which can be used to locate the next level of component. Components can be ROM tables again, or individual components. Provided the system complies with the rule that each component is only referenced once in the ROM tables and there are no loops, it is possible to identify all the debug components which are accessible to each debug agent.




Processor debug and monitoring features


The exact features vary between processor design, and can also vary from one implementation of a processor to another. Processors typically provide a halting debug mode (where architectural state can be observed) and single step execution. Also common are breakpoint units and Performance Monitoring Units (PMU). CoreSight provides an Embedded Cross Trigger mechanism to synchronize or distribute debug requests and profiling information across the SoC.



Cross Triggering

CoreSight Embedded Cross Trigger (ECT) functionality provides modules for connecting and routing arbitrary signals for use by debug tools. Wherever there are signals to sample or drive, a Cross Trigger Interface (CTI) is used to control the selection of which signals are of interest. Most systems will implement a CTI per processor, and at least one CTI for system level components. The CTIs in the system are interconnected using a Cross Trigger Matrix (CTM) which distributes any selected input events across the SoC to every CTI. Each CTI is programmed to use these distributed events to drive local control signals.

For processors and ETM trace units, the event connections to the CTI are standardized (although this does vary from processor to processor, as described in the processor documentation). Typical connections are listed below.







Example use case

Trace logic External Outputs (4 bits)

CTI Trigger inputs

Trace logic resources to trigger trace capture or debug

Trace logic External Outputs (2 bits)

PMU inputs

PMU counters to extend trace logic counters

PMU Events (~30 bits)

Trace logic External inputs

Filter trace based on processor events such as cache miss

PMU overflow

CTI Trigger inputs

Forward PMU counter overflow to interrupt controller or other clusters

Processor Debug Restart

CTI Trigger input

Synchronized debug restart across clusters (supporting halt and restart)

Trace Buffer Full

CTI Trigger input

Halt processor on trace buffer full

CTI Trigger Output

Processor interrupt input

Cause interrupt based on input to CTI or other CTI in system

CTI Trigger Output

Processor Debug Halt Request

Enter debug state based on input to CTI or other CTI in system

CTI Trigger Output

Trace Port Trigger request

Indicate trace trigger to trace capture device

Table 1 - Cross Trigger Connections




Trace Sources

CoreSight technology provides a standard infrastructure for the transmission and capture of trace data (presented as arbitrary streams of bytes). This allows for optimum sharing of common resources. Various trace sources are available:



Processor Trace Units

Processor debug is implemented by Embedded Trace Macrocells (ETM trace unit) or Program Trace Macrocells (PTM trace unit) depending on the target processor. Each ETM trace unit or PTM trace unit is specific to the processor it is designed for.

The feature set varies depending on the use cases anticipated for the different processors, but all CoreSight ETM and PTM trace units which use an AMBA Trace Bus (ATB) output can be combined in a system. Trace units might support the following:



  • Processor execution trace in varying degrees of detail
  • Resource logic, often useful as an extension to processor performance monitoring resources
  • Filtering logic to reduce the amount of non-interesting data which is captured


A common feature of trace units is efficient compression and encoding, relying on a copy of the executed code for decompression. Using halting debug, it is possible to extract the code image from program memory.




Instrumentation Trace Units


The instrumentation trace and system trace units provide the ability for running software to be instrumented with messaging (either by the programmer, or through a tool flow). This is more intrusive than using processor trace, but provides information at a higher level. The instrumentation trace macrocells are typically mapped into system memory. Tightly coupled Instrumentation Trace Macrocells (ITM) exist for some processors, the System Trace Macrocell (STM) is a more generic version which can be used in any system.




Trace (ATB) interconnect


One advantage of using a standard trace bus protocol is that a small set of modular components can be used to generate sophisticated trace infrastructure. These components include bridges for timing closure, clock and power domain crossing, replicators and funnels which can be used to combine data streams, and buffer components. Upsizers and downsizers are used to convert busses of varying data width. A key feature of the AMBA Trace Bus (ATB) is that the trace source identification is passed with the data, permitting cycle by cycle interleaving of trace data from different sources. CoreSight trace interconnects provide the following features:

  • Backpressure to stall a trace source based on the ability of downstream infrastructure to collect data
  • Flushing of any data stored in intermediate buffer components through the interconnect
  • Transfer of byte orientated data, agnostic to the underlying data protocol
  • Synchronisation request distribution




Trace Sinks


A trace sink is the final CoreSight component in a trace interconnect. A system can have more than one trace sink, configured to collect overlapping or distinct sets of trace data. Trace sinks can stream data off chip, provide a dedicated buffer, or route trace data into shared system memory. These different solutions cover a wide range of latency and bandwidth capabilities




Stay tuned for my next blog which looks at processor trace architectures and debug access ports. If you have any questions then please leave a comment below, I'll get back to you ASAP!

‘I can hear it buzzing in the air tonight …’ Ok, so I took a little poetic license with the lyrics of Phil Collins’ classic hit ‘In the Air Tonight’, but it made for a more interesting opener than ‘Hi, my name is…’. What is this guy droning on about you may be asking. Sit tight…


This week at Freescale FTF Americas 2015, our new Kinetis V series of ARM® Cortex®-M class MCUs set embedded motor control on a new heading. With thousands of discerning customers to impress, Freescale sets the bar high when it comes to FTF product demos and ‘cool’ factor tops the requirements list. Freescale’s motor control demo vault is filled with a vast array of industrial and appliance type creations as those have historically represented the biggest slice of the motor control pie. While such demos have performed admirably for many years and continue to do so, we thought that it was time to look further afield for an application befitting of our first ARM-Cortex-M7 based MCU and FTF’s 10-year anniversary. Motor control is after all, the largest consumer of electricity on the planet so presumably there must be an unknown talent out there just waiting for its turn in the FTF spotlight.

Men-less machines

After many hours of coffee and doughnut fuelled deliberations, the demo team settled on a drone. Why drones? The short answer is “because washing machines don’t fly very well”. No, in all seriousness there are a number of reasons why the drone, UAV or quadcopter was deserving of its place. Firstly, it ticks the ‘cool’ box. Defying gravity is always a neat trick but it now comes with added flair with drones now able to perform all types of aerial wizardry. Secondly, spinning multiple motors accurately is a task that our Kinetis V series MCUs take in their stride so it showcases the MCU’s talents to good effect. Technical prowess box ticked. Thirdly, is the potential business opportunity associated with it. What began as a hobbyist play-thing is now rapidly transitioning into a viable commercial market of sizeable proportions and increasingly diverse end applications. These magnificent “men-less” flying machines are finding new destinations on an almost daily basis including aerial surveying of structures and farmland, cargo transportation to remote communities, and even shark spotting in California. The market is still at an embryonic stage with many regulatory hurdles to clear, but all the signs are that it won’t be long before drones will be delivering pizza to your house (hopefully not dumped on your roof ‘Breaking Bad’ style). In short, this application is….wait for it…..taking off.

4 x 8-bit MCU = 1 x 32-bit Kinetis V MCU

When it comes to motor control, Freescale’s expertise is par excellence. Naturally I’m biased, but decades of new product development, turn-key customer projects for the industry’s ‘big players’, and a vast library of sophisticated enablement software speaks for itself. With that in store and Kinetis V series MCUs ‘straining at the leash’, the drone demo project was seized upon. Against an aggressive schedule – typical of every trade show demo request from marketing I expect – the development team was set in motion. Motor control passions were ignited and soon propellers would (hopefully) begin turning.

The drone selected was the DJI Phantom1 – a workhorse of the market and hence a suitable platform with which to test our V series MCU’s credentials. Propeller guards were also purchased to avoid any unfortunate finger incidents – 8K rpm blades can cause quite a nip.


The Embedded Speed Controller (ESC) modules were the target area – four per drone and each controlled by one 8-bit 8051 MCU. A new consolidated ESC design was manufactured using one KV5x ARM Cortex-M7 MCU where previously there had been four 8-bit MCUs. Leveraging the MCU’s agile performance and highly integrated motor control peripherals – 240MHz ARM Cortex-M7 core, high resolution PWMs, multiple high speed ADCs (5Msps) and its inter-peripheral crossbar – a four off 6-step BLDC control system was implemented. This required approximately 50% of the KV5x MCU’s CPU performance leaving additional bandwidth to implement field oriented control (FOC) and flight stability control functions in future ESC designs.


An additional KV4x ARM Cortex-M4 version of the ESC was built to demonstrate the unique scalability that the Kinetis V series brings to this and countless other motor control applications. One MCU family – multiple end products, with scalable form, functionality and price.

By coincidence, the demo team discovered a parallel drone project using the Freescale Analogue Product Group’s new gate driver IC. A quick decision was made to join forces and include the GD3000, adding further power control capability while replacing several additional discrete components. More BOM cost reduction. With schematics drawn up, PCBs populated and software tested, the result was 2 new custom made ESC modules, and thankfully no missing fingers.


Drone 2Drone 1


Up, up and away

The Kinetis V series drone made its maiden flight in the TechLab of Freescale FTF Americas 2015. Unfortunately, for logistical/safety/legal reasons, drones can’t be flown freely in such built up areas (hotels owners aren’t keen on drones ‘buzzing’ their elaborate ballroom chandeliers), hence it was temporarily caged it within a safety cabinet. However, it won’t be long before it’s fully airborne and appearing on the Freescale Internet of Tomorrow Trucks, at Design with Freescale seminars and at multiple other locations around the globe. So look out or should I say look up, for a Kinetis V series drone coming to a city near you soon.

It is often said that the best things in life are those that move us. While my pun-infused ramblings might not, I’m fairly confident that the Kinetis V series will. If not, try Phil


Danny Basler is a product marketer in Freescale’s Microcontroller Product Group

William Orme of ARM, Nick Heaton of Cadence Design Systems and Brian Choi of Samsung Electronics all participate in a panel discussion on 'How to address the challenges of IP Configuration, SoC Integration and Performance Validation', hosted by Sean O'Kane at the Chip Estimate booth at 52DAC this month.


In a forthright and honest discussion, the three talk about some of the challenges related to SoC design, including the fact that SoCs are increasing in size and complexity, as well as the rise in modular subsystems and virtualisation.


Brian is a principal engineer at Samsung working on SoC integration with a focus on improving the design cycle, making the validation of a SoC faster and better. He also has previous experience as an SoC architect. In the discussion he shares that for Samsung in the mobile market, customer requirements can change quite a lot over the course of the project, which naturally causes a change in the specs, even halfway through the chip being built. We need a methodology that incorporates new IP during a project and means you don't have to start again from scratch. It’s a challenge right now for silicon providers and OEMs.


Nick is a distinguished engineer wtih Cadence R&D, working on architecting and innovating products that help in the SoC space. He has a background in advanced verification and has been looking at applying technologies to SoC integration to help solve that problem. One of his key points from the discussion is that timescales have stayed the same for design projects over the last 5-10 years: 6-9 month projects even though the complexity is growing massively. Naturally that has an effect, as with the shortening cycle of IP release it puts so much pressure on handling this complexity and getting the integration right the first time to avoid unnecessary and costly waste.


William has a long background with ARM, beginning life as a hardware design engineer before spending some time doing software design and now has a strategic role within System IP marketing, looking after product lines such as interconnect, debug & trace and IP tooling. As a way of solving the problem, William notes that we have moved to an adoption of IP standardisation. Using intelligent system design tools we can now reflect the configuration state of the IP and are able to share this with tools vendors, verification and other stakeholders to make the design process faster.



On IP configuration - "we want to abstract away a lot of the details as things get more complex, use algorithms that embody the design intelligence to attack the complexity issue."

On IP integration - "algorithms can help shape what Brian spoke about in terms of changing specs and design reuse. You can create the algorithm and design rules to check that the configurations match across different views, for properties and interfaces etc, and if they fir the requirements, and show users what has been set up in a way that can actually be understood through visualisation like schematics, micro-architectures and so forth."


Find out more in the full video of the discussion below








I hope you enjoy, and leave any comments or questions in the sections below

Without motor control, our homes and lives would be far less convenient than they are today – we’d still be washing our clothes by hand, cooking over open fires and desperately searching for the nearest ice cave in which to chill our beers. Outside of the kitchen the effect would be equally troublesome – HVACs replaced by hand fans, garage door/gate opening would require manual labor (shriek with horror!), and filtering the pool/jacuzzi would take months with only that lukewarm beer in hand to dull the pain. Jokes aside, motors are a BIG deal and represent a huge area of opportunity for electronic control using microcontrollers (MCUs), which bring increased automation and energy efficiency benefits to the appliance.

Within such applications, the MCU performs several functions. Its timers generate up to 6 channel PWMs which drive, via an inverter stage, the AC motor’s 3-phases that essentially make the motor spin. Analogue to Digital (ADC) module(s) are used to measure the various phase currents to track the speed and/or position of the motor as it rotates, known as sensor-less feedback control.

Several household applications also use 2 motors: washing machine (big drum and pump), dishwasher (sprays the water and drains), fridge/freezer (compressors, air-flow to stop frost), and HVAC/air conditioner (compressors and air flow). Many MCUs contain two sets of 6 channel PWMs allowing them to drive two inverter stages and in turn spin two motors. Generally, the sensor-less monitoring of speed and position is completed using one or two ADC modules. Sensor-less speed algorithms work with less errors if they can simultaneously acquire two of the phase currents at specific times of the PWM period, but error adjustments can be made if only one ADC module exists, and the two phase currents are measured back to back. For driving a dual motor control application with two ADC modules, the application can assign one ADC per motor and include some error correction in the speed calculation. Alternatively, the dual motor drives can be synchronized by having one set of PWMs 180 degrees out of phase from the other, and making use of both ADCs for both motors by assigning different input channels. An MCU with four ADC modules allows true, independent dual 3-phase motor control which helps simplify application code and minimizes acquisition errors. The trade-off that often arises in such integrated solutions is the cost of having four ADC modules, versus the level of power efficiency savings that will impact the end consumer.


The latest member of Freescale’s fast emerging Kinetis V series of ARM® Cortex®-M class MCUs – the Kinetis KV5x MCU family – is well equipped to handle the demands of multi-motor applications. With multiple timers, four high-speed ADCs (sampling at up to 5 Msps), and a 240MHz capable Cortex-M7 core, fully independent sensor-less control of two 3-phase motors can be accomplished with ease. With CPU MIPS to spare, the KV5x MCU can also perform other functions including adding secure internet connectivity via its on-chip Ethernet, multiple CAN and UARTs, and Encryption modules. With the embedded market currently ablaze with IoT (Internet of Things) concepts, the opportunity to remotely monitor and manage countless motorized appliances in the home and beyond can now be realized from the comfort of our armchairs, workplaces or further afield. So you can rest easy, thanks to the humble MCU it should be some time yet before we need to search for that elusive ice cave.

To learn more about Freescale’s motor control solutions, Kinetis V series MCUs, visit: freescale.com/Kinetis/Vseries


Dugald Campbell is an MCU systems architecture engineer for  Kinetis MCUs

The Freescale Technology Forum (FTF) has always been one of my favorite events and this year was certainly one to remember. FTF 2015 was held in the music capital of the world, and Freescale's own backyard, Austin Texas. There was a great mix of technical tracks with over 350 hours of technical content, a fantastic keynote speaker in Steve Wozniak, live music, and of course lots of fantastic ARM technology!


Freescale has one of the broadest ARM portfolios ranging from some of the smallest 32bit micro-controllers (KL02) all the way up to the latest ARMv8 64bit Cortex-A57 based devices (LS2080), and everything in between, all being showcased in the technology lab. Here are a few of my favorite demos:


Freescale Kinetis V MCU family

Freescale have just recently launched the newest member of the Kinetis V family, the KV5x MCU. The KV5x implements the Cortex-M7 processor and targets Motor Control and Power Conversion applications. There were several demos showcasing the KV5x, by my favorite had to be the quadrocopter where a single KV5x was being used to control all 4 motors. Unfortunately I wasn't allowed to fly it, probably to the benefit of everyone in the tech lab! There was also another KV5x demo where Freescale was showcasing the Kinetis motor suite which can be used to simplify the development of advanced motor control functions. Using the Kinetis motor suite I was able to successfully use a KV5x to drive a washing machine motor simply by following the on screen prompts!




Networking with QorIQ Layerscape

There were a lot of Networking demos on display in the tech lab including one demo showing 2 of Freescale's new ARMv8 based Layerscape parts; the LS2080, and LS1043. The demo allowed you to run benchmarks on one or more CPUs and displayed the benchmark result as well as the power consumed during the run. The best part was that the demo allowed you to set the number of cores used to actually run the benchmark, which in turn allowed you to observe the power consumption of the CPUs. Is was great to see that enabling a second Cortex-A53 had less of an effect on power consumption than the variation in successive demo runs. Also seeing the raw performance of 8 Cortex-A57s was equally impressive.




Internet of Things - Devices and Gateway

I also found the LS1021A-IoT Gateway demo interesting as it showcased how an ARM powered IoT edge devices such as a Freescale Kinetis based device can talk to an ARM powered LS1021 gateway. This demo really drove home the fact that the IoT is being enabled by ARM technology.



Automotive Vision Processor - Heads Up Display (HUD)

Freescale are one of the largest providers of Automotive semiconductors on the planet and ARM is well represented in Freescale's automotive product portfolio. The newly announced Cortex-A53 based S32V vision microprocessor was on display in the tech lab as well as the Cortex-A5, Cortex-M4, and Cortex-M0+ based MAC57Dxx which was powering an instrument cluster with a secondary display for powering a windshield HUD.




And lets not forget the ARM Booth where we displayed the latest in ARM development tools working with lots of new Freescale silicon. My favorite demo was DS-5 displaying heterogeneous debug support for both the i.MX 6 Solo X as well as the i.MX 7.





And lets not forget the no-hands race car simulation inspired by Arrow's Sam Car which really stole the show!




There were so many more great demos, and I haven't even gotten to the ones in the IoTT truck that was parked around back! With this much going on, it is easy to get overwhelmed. Luckily for us, Freescale make their keynote and technical session content available after the show via their FTF site linked below.


FTF 2015 | Freescale Technology Forum - FTF 2015

ARM senior product manager Simon Rance speaks with William Orme about the ARM® Socrates™ IP Tooling suite at 52DAC in the Moscone Center. Comprising three tools, CoreSight™ Creator, CoreLink™ Creator and Socrates Design Environment, the IP Tooling suite helps partners configure and integrate their SoC quickly and efficiently. To find out more please visit - IP Tooling - ARM







If you have any question or opinion about this video please leave them in the comments section below and I will respond as soon as possible.


Further info:

System Assembly through Intelligent Configuration

New ARM IP Tooling Suite Reduces SoC Integration Time from… - ARM 

Whitepaper: Lessons from the field - IP/SoC integration techniques that work.docx

Whitepaper - IP-XACT Standardized IP Interfaces for Rapid IP Integration 

White Paper - Solving Next Generation IP Configurability

IP Tooling - ARM

ARM’s VP of System IP marketing Andy Nightingale presents the new ARM® Socrates™ IP Tooling suite at 52DAC in the Moscone Center. The tools, CoreSight™ Creator, CoreLink™ Creator and Socrates Design Environment, help partners configure and integrate their SoC quickly and efficiently. Andy explains how the tools use IP-XACT and an instruction-based methodology to deliver an 8x improvement in the design schedule. To find out more please visit - IP Tooling - ARM









Do you have any questions? Please put them in the comments below

Last week I attended the Design Automation Conference as an intrepid reporter to put my ear to the ground and take note of what is happening in the industry. I wrote some daily review blogs of my time on the show floor (which can be seen here, Day 1, Day 2, Day 3) but I have come up with some talking points from the conference. These are the topics that I found got most air time both in the booths and in the many speeches, presentations and panel discussions across the week. Let me know what you think about them in the comments section below.



**Some video highlights of presentations and panel discussions from the show**


Video: ARM at 52DAC - Socrates IP Tooling

Video: ARM at 52DAC - DS-5 Development Studio

DAC 2015 IP Talks ARM Panel   Panel discussion between ARM, Samsung and Cadence

Video: Introduction to ARM Socrates IP Tooling





Relentless collaboration

On Tuesday morning the VP of Samsung Electronics Foundries gave an insightful presentation on their advancements over the past 12 months and their vision for the foreseeable future. His words carry an extra amount of weight when you consider that in 2014 he promised 14nm silicon in a year’s time and was able to deliver on his word. It was not done in a silo however, and the phrase he used of “relentless collaboration” between EDA, IP companies and foundries is absolutely crucial to marching on with the progress he outlined, of seeing silicon for 10nm in 2016. The other key point he made was that each foundry process must be aligned to and optimized for the target segment. For example reducing the process node for server density and mobile, but there is still plenty of innovation at higher nodes for automotive, wearable and of course IoT. The same breakfast session showed proof of what can happen when partners collaborate. ARM®, Synopsys and Samsung managed to implement a quad-core Cortex®-A53 processor design with CoreLink™ CCN-502 designed for networking on a 14nm LPP process in a timescale of just four weeks.




Automotive tech is at a tipping point

Tipping points was my theme of day 2 at DAC and this is encapsulated by the automotive presence last week. There were some fascinating displays that could truly change the way we travel forever. Cadence Design Systems CEO Lip-Bu Tan is looking forward to self-driving cars so that he can get even more work done, but for the rest of us mere mortals it will also mean lower fuel costs, lower emissions and most importantly fewer lives lost due to accidents. With a mission statement like that, Jeffrey Owens had everybody on tenterhooks as he explained how Delphi Automotive were working to make this a reality. A combination of software, mapping, visual camera system and connectivity with other vehicles on the road were how his company tinkered with an Audi QS5 and managed to make the 3,400 trip from coast-to-coast in the US, 99% of which was done without any human interaction. The first step is always the hardest, and getting autonomous vehicles from the current stage to commercially viable is the next chasm that automotive manufacturers need to cross.

Delphi.jpgAutomotive tech has massive possibilities in the coming years




IoT needs to go hand in hand with networking capabilities

Speaking of the internet of things, the revolution may feel like it is stagnating somewhat as initial excitement fades during the period where we are still waiting for killer apps to delight the imagination. However in the design community it doesn’t mean that people are waiting for that to happen. The recently-announced ARM Cortex M subsystem for IoT is one way, reducing the risk and time involved with chip design for IoT devices. On the other side of the equation, a number of presentations focused on the construction of networking infrastructure to provide capability for when the world becomes a whole lot more connected with all of the extra embedded devices. ARM’s Wolfgang Helfricht captured the general mood by saying that across the world the networking infrastructure needs to significantly increase in bandwidth. Equally as important, wherever possible the processing of information should happen at the edge in order to reduce traffic congestion across the network. This will put more responsibility on sensors and end devices to analyze and process data.



Networking trends.png


When hardware met software

It’s been a talking point for a number of years that system performance requires a high level of integration between hardware and software. Right across the week, from exhibitors, panellists, demos and keynotes, people have been keen to talk about software. The software side of SoC development has gone beyond a minor concern to a real area of differentiation. There are some key similarities (numbers of lines of code compares to gate count, exponential complexity) and differences (software doesn’t have the same up-front quality testing before it is released, but can be fixed with a patch) but the key message was the same: for a system to work optimally you need a marriage between both sides. What surprises me is that it has taken this long for people to properly address the need to work on this relationship.

The future is coming, and it's smaller!

There is only one thing more important than the present in the semiconductor industry, and that’s the future. Roadmaps are extremely du jour as everybody wants to make it clear that the current state of affairs is only a stepping stone to the next generation of improvements. Foundry representatives were extremely bullish about the timescale for delivering smaller nodes, and it will be based on the day-to-day engineering innovations that all add up to great achievements. Whether it’s Samsung talking about 10nm silicon or keynote speaker Vivek Singh talking of advanced research going into 7nm, it seems like the future has no end in sight.




Months to days

Speaking of the present for a second, it was agreed that one of the major highlights of the show was the new ARM Socrates IP Tooling suite. Released last week, they are already able to prove an 8x schedule improvement on ARM’s internal reference designs and caused a lot of excitement for visitors to the ARM booth.





It’s been one of the biggest trends in the EDA industry over the past decade, highlighted again by the announcement last week that Synopsys are to acquire Atrenta in the coming weeks. As the industry matures, consolidation will only continue to happen and it was forefront in the thoughts of both Aart de Geus and Lip-Bu Tan when they spoke at the conference. The Cadence CEO listed the trend for consolidation as one of his major worries as it can often stifle innovation, while the head of Synopsys said that it is only feasible when it makes sense in terms of technology and economics. I get the sense that consolidation will continue as larger companies seek to differentiate and enter into new markets through the acquisition of smaller companies and startups.




To finish things on a personal note, I was naturally excited to get out and see some sights in the city of San Francisco. I was given a strong recommendation to visit the Cliff House and taste some of their famous clam chowder (which lives up to its reputation). However the 5 miles from downtown to the coast brought with it a sharp decrease in temperature as the fog took over. It reminded me of a quote from the veteran Mark Twain, "The coldest winter I ever spent was a summer in San Francisco".


Do you have an opinion on any of these topics? Please let me know by leaving a comment

The ARM Connected Community took to the road last week at DAC in the Moscone Center in downtown San Francisco. A total of 10 partners were showing demonstrations of how their products helps optimize ARM technology, from a range of development tools to software and performance modelling. In the interest of making sure our online community members get the full DAC experience, I spoke with each partner to get an explanation of what they were demonstrating to people who stopped by. I found it very interesting to talk with our partners who come from a variety of backgrounds and all contribute greatly to adding value and choice to SoC designers within the ARM ecosystem. I also caught up with some of my ARM colleagues who were exhibiting at the show to get a handle on what exciting technologies ARM was exhibiting this year.



Prithi RamakrishnanCordio Radio IP


Prithi - Cordio.jpg


This week we're showing off the Cordio Radio IP that reduces the power consumption within microcontrollers. There is a huge growth in radio IP at the moment as Bluetooth continues its popularity as a communication medium for mobile and particularly embedded devices. One of the examples of this is in the Cortex M subsystem for IoT that was launched last week. Here we’re showing off the subsystem in a device that can register the presence of a hand and the temperature of a room. It could work as a home security system for example.





William Orme - ARM Socrates IP Tooling


William and Simon - Socrates.png

Last week ARM officially launched the Socrates IP Tooling suite, and we are here to demonstrate the tool to partners. We are walking people through the tool to show them just how easy and quick it is to configure and integrate ARM IP to generate an optimized SoC. The CoreSight Creator tool that I'm showing here represents a huge shift from how partners used to configure their CoreSight debug and trace subsystem, and reduces the time it takes from months to days.





Ronan Synnott - ARM DSG Group


In this demo we're running Android on our Juno platform so we can play Angry Birds . You can see on the other screen that we have the Juno platform hooked up to Streamline within DS-5 and it is constantly monitoring the performance profile of the CPU on the platform. Within the game it’s quite low usage and run within the cache but we can see that when you load a new level there is a short spike in CPU load. It's a simple way of showing how CPU loads differ across different use cases and at particular times.




NetSpeed Systems




We make an interconnect product that helps maximize the performance of the ARM cores. We’re still quite a new company, founded in 2011, so we find that the ARM Connected Community is a great way to discover what’s going on in the system design community, and interact with other companies within ARM’s ecosystem.










We have a tool that helps with the creation of the spec for SoCs designed with the IoT market in mind. It’s quite a new tool as we were involved in other markets before this so we are hoping to help developers of ARM-based IoT devices with their time to market.










We make an interconnect product that helps to reduce the time it takes for CPU clusters to communicate with the rest of the chip. We’re also showing an OCP Library for Verification that enables core designers to validate their OCP socket interfaces and maximize performance.





Mentor Embedded


Mentor Embedded.jpg


We make optimal use of the latest multi-core and heterogeneous SoCs to deliver reliable safe and secure systems that incorporate rich graphics and connectivity with a customizable Linux® solution, the low power capable Nucleus® RTOS, and a high performance Type 1 Hypervisor. They are particularly applicable to the automotive market in this regard.






Mentor Graphics


Mentor Graphics.jpg


This week at DAC we have a pretty large presence, with our own booth and a Functional Verification Academy. On the ARM Connected Community booth we’re showing some of our tools focused on IC design, place & route and physical verification. We work closely with ARM to make sure that our tools are aligned with the way people want to design their SoCs.









To properly implement an SoC you need more than just high quality IP. That’s why Synopsys works closely with ARM to provide a wide variety of tooling solutions to accelerate innovation throughout the design flow for ARM-based SoCs. This week we’re showing how our new IC Compiler 2 works to make the place & route process even faster.






Carbon Design Systems


We run performance models for hundreds of different IP configurations and SoC setups. Because we have over 10 years experience of doing this we are now able to make suggestions about what works best together depending on the IP customers are using and the PPA considerations they have. Another way that we work together with ARM is via our Swap and Play functionality that interacts with the Fast Models. Fast Models are really great because they work quickly, and what our tool does on top of that is allow users to stop the cycle at any time and get detailed analysis of a particular point they are interested in. Most system designers and architects know what area they are looking to optimise so it’s a case of providing them with the tools to really dive in deep and get precise information about what’s going on and how to maximise the performance.








We are directing our attention to the mobile, cloud and connected devices market with solutions that try and solve capacity challenges within mobile. We are most known for memory technologies such as DDR4, we make the bus architecture for that. This week we’re also showing some security solutions as this is a major trend we are seeing in the industry. Our DPA resistant cryptographic cores and software libraries are an easy-to-integrate solution.








We do simulation software to enable chip companies deliver SoCs that are optimized across performance, energy and cost. The demo we’re showing here displays some of the things you can do with our software, like signal integrity analysis, thermal management and reliability sign-off.





Imperas Software




We make high-performance software simulations, such as embedded software development and debug and test solutions. At this show we’re showing off a demo about how our software can be used to deliver embedded Linux. We’re also showing the full line of Open Virtual Platforms models of ARM processors, including Cortex-A, Cortex-R and Cortex-M families.










We provide an Amazon-style service to those who wish to build SoCs. We have a large catalog of IP and we provide a service by giving people all of the options for different IP blocks when they are in the decision stage. With our experience we are now able to make suggestions based on what has worked very well for our customers in the past, as we know which IP components work exceptionally well together.










We make tools that are used with the development of ARM-based embedded SoCs. We have been supporting ETM for over 10 years and at this stage have some extensive analysis capabilities for diagnosing on-chip bugs. The Connected Community works in our favour as we can see what issues ARM partners are having, join in discussions and tell the world what we have been doing as a company.




Thanks for the attention! If you want to read a recap of the daily events at DAC then you can find them in the links below:


DAC Day #1: Samsung Innovation, EDA Acquisitions, and Magic Tricks

Day 2 at DAC: Tipping points, automotive and networking

Day 3 at DAC: Kitchen windows and cyber security

The Denali party by Cadence at Ruby Skye was, as always, the social highlight of DAC last night. Rocking away to the 70’s classics by the house band it inspired a few of us to go back in time and don some 70’s fashion in the photo booth! For the sake of decency I’ll not show you the results Here's a more suitable photo


Denali.jpgThe wristband needed to gain access to Ruby Skye for the Denali Party by Cadence


Between that and the Stars of IP party that was held on Tuesday night as well, the show floor was certainly quieter this morning as a result of people enjoying themselves last night! Needless to say this intrepid reporter was up and bright in time to be ready for the keynotes that started at 9am.


The main theme of today for me was security. It’s a growing concern in the system design community across a range of segments, from IoT to automotive and even servers. It’s been one of the key areas that this year’s DAC has addressed and it literally took centre stage on Wednesday with a keynote discussion on cyber threats to connected cars. Craig Smith of Theia Labs and Jeff Massimilla of General Motors spoke at length about the fact that cars are networks on wheels, and they should be secured as such.


We heard yesterday that OTA updates for cars may be available as soon as 2016. Today that vision was expanded, whereby updating your car’s software could become as routine as getting an oil change. The potential this brings for making the driving experience a whole lot safer is huge. However the cynic in me thinks of the way cars are now nigh-on impossible to take care of DIY style, and I imagine even tiny software updates may require a trip to an OEM-approved mechanic.


Jeff Massimilla made a good point about the need to get ahead of the curve on cyber security for cars. If attacks start coming in at a greater level than security then it would be devastating to the whole movement, as people would (justifiably) lose trust in the machine and the software. When you consider the predictions that automotive will become a $240b industry by 2020 then every manufacturer will need to make sure their connectivity is secure from hacking.


Mclaren.jpgOEMs such as McLaren are investing heavily in cyber security for their vehicles (here on IC Manage booth)


All the talk of security reminds me of the history of locks. In the entire history of mankind there has only been a brief period, 70 years in the 18th and 19th centuries, where you could put something under lock and key and have complete, unwavering certainty that no intruder could get to it. Since the 1850’s, the feeling of ‘perfect security’ has remained elusive. With that said, the speakers were in consensus that it’s important we differentiate between real auto security threats and unwarranted ones. The latter have the potential to spread panic and misconceptions if not addressed quickly.


Security was also on the mind of Synopsys CEO Aart de Geus who was forthright in his conversation with Ed Sperling at the DAC booth. Talking about differences between hardware and software, he mentioned two key areas. The first is that software isn’t subject to the same rigorous standards as hardware; if an error is found in a product you can patch things quite quickly, but with patch after patch things can increase in complexity.

Also, in terms of software security you have people who proactively try to hack software, which doesn’t happen with hardware. When asked about IoT, he likened it to putting kitchen windows into a bank vault. A vault should only have one door, a pretty thick one, and these small devices are essentially punching holes in the security of the network. Unless something is developed and standardized across all endpoints as a minimum, the security of the entire network can become compromised. Similarly, there have been examples of some enterprising criminals smashing the tail light of a car and gaining straight access to the bus that way. As the level of connected devices in the network rises, significant challenges with security are appearing. As a positive example he singled out ARM’s TrustZone, which has been built up systematically to build trust with partners and their own experience in developing highly secure systems. In terms of where it fits in, security is an angle in the software space and can actually be considered as a part of the quality assurance of the software in best practices.


Aart de Geus.jpgEd Sperling and Aart de Geus discussed security, a major theme at this years DAC


The last day of DAC52


And so with that the DAC exhibition is over for another year and will be moving to Austin in 2016! For those who are sticking around tomorrow there are still conference events underway in the meeting rooms, like the designer track. Here are some of the standout talks:



  Tomorrow I’ll bring you a highlight of the ARM Connected Community partners, and give them the opportunity to give some insight on their experience of the show.

We all live in the 21st century, meaning the majority of communication takes place via email, telephone or even blogging. With that said I have enjoyed putting a face to the name of a lot of ARM employees at the booth. I spoke to a colleague yesterday about the excellent Malcolm Gladwell book ‘The Tipping Point’, which really foreshadowed the theme of today’s events at DAC.


After my first day at DAC, Day 2 dawned and brought with it a whole new range of topics to sink my teeth into. Jet lag reared its ugly head and had me wide awake at 5am but this was actually perfect timing to swing by the ARM Samsung Synopsys breakfast. The lavish ballroom of the Park Central Hotel played host to a great session that gave insights into future networking, foundry and implementation. The session kicked off with ARM’s Wolfgang Helfricht talking about future networking evolution and he had a couple of key points that were quite telling:

40% of IoT data will be dealt with and analysed at the edge, meaning that data does not need to travel all the way to a datacenter and thus freeing up networks.

The other insight he had is that we will soon reach a tipping point in IT networks, and today’s excess networking capacity will be tomorrow’s bottleneck due to the infrastructure becoming overwhelmed. Therefore there is a need to invest in new, state of the art networks and datacentres in order to increase the grid’s capabilities to deal with the IoT revolution when that takes off.


ARM SNPS brekkie.jpg


Indeed, Cadence CEO Lip-Bu Tan mentioned during his fireside chat that datacenters are his hot tip for investment, that there is much growth potential there.

The session went on to show how the three companies collaborated to implement a Cortex-A53 processor with a CoreLink CCN-502 cache coherent network on Samsung’s 14nm LPP process in just a timeframe of 4 weeks! When people speak about short design cycles in SoC development it is normally in the mobile space but this shows that it is not just limited to that. One of the key arguments Malcolm Gladwell makes is that revolutions generally take longer to happen than you initially anticipate, but when it takes off then change happens much more rapidly than you would imagine. With that said, demonstrating the fact that a networking layout can be put together so quickly is a critical step in putting in place the networking infrastructure that will support the IoT revolution.



With that I ran across the street to make it in time for the morning keynote by Jeffrey Owens of Delphi Automotive. This is the conference event I was looking forward to most since the lineup was confirmed a few weeks ago as I have a big personal interest in automotive tech. Designing SoCs for automotive brings a lot of unique challenges, in a field where the difference between life and death is so small, the validation and quality assurance needs to be absolutely bulletproof for it to be accepted. To a certain extent this means that the pace of advancement can be hindered by security concerns but listening to Jeffrey would make you believe that even with the heightened quality requirements the velocity of innovation has not been stopped.




Listening to him speak, you get the feeling we are on the cusp of automobiles taking off in terms of technological advancements in three key areas; Safety, Green and Connectivity. While the opportunities here are massive, the automotive industry faces challenges keeping up with all of them and that's where it leans on the support provided by the design automation community to deliver on the potential for advancement that is out there. One of the major obstacles to this is software, and getting it to a release-quality level for the automotive industry as there can be no room for error.

Looking ahead, he spoke of OTA (Over The Air) updates for cars arriving as soon as 2016 which would go a long way to future-proofing the next generation of automobiles. Speaking of automotive, I have to give credit to Real Intent for having the best booth attraction at this year’s DAC! They have two driving simulators that allow you to try and beat the AI (in a case of human against autonomous vehicle) or challenge someone else to a race. From my own experience, the computers still have a bit of catching up to do before they drive faster than me


Driving simulator.jpg


After a whirlwind morning of presentations and keynotes I took some time to breathe before checking out the ARM Connected Community booth. On Thursday I’ll bring you a full description of all the ARM partners on the booth but here’s a sneak preview with ARM's Ronan Synnott.




"In this demo we're running Android on our Juno platform so we can play Angry Birds . You can see on the other screen that we have the Juno platform hooked up to Streamline within DS-5 and it is constantly monitoring the performance profile of the CPU on the platform. Within the game it’s quite low usage and run within the cache but we can see that when you load a new level there is a short spike in CPU load. It's a simple way of showing how CPU loads differ across different use cases and at particular times."


In the afternoon one of the highlights was the ChipEstimate.com panel discussion featuring William Orme, Nick Heaton (Cadence) and Brian Choi (Samsung) on IP configuration, integration and validation. Nick joked that ARM designs IP that is configurable, Samsung suffers the headache of attempting to configure it and Cadence attempt to solve this issue with their tools. It's yet another example of the large-scale collaboration that you see going on here at this event.




Today I got a sense of the design automation community’s unspoken mission, to build the future. Between looking at the engineering opportunities and challenges in networking and IoT to how automotives are quickly becoming the most powerful supercomputers, it seems that technological advancements are happening beyond the consumer sphere. To paraphrase a famous quote, day 2 of DAC was one of glimpsing the future and seeing just how it will work.


So tomorrow is the last day of DAC exhibitions, but there is still plenty happening on the show floor and at the conference. Here are some of the events I’m looking forward to:

  • Keynote on cyber threats to connected cars - 9am – Gateway Ballroom
  • Aart de Geus chat - 11.30am – booth 311 – especially after Lip-Bu Tan’s enlightening and frank discussion on the EDA industry, semiconductors and giving his own investment tips, for which he held a crowd of 60 people raptured, I’m equally looking forward to this talk from the Synopsys CEO

2015-06-07 11.22.08.jpg


A ticket to the Moscone Center in the beginning of June is so sought-after that some attendees even decided to camp outside from Sunday afternoon onwards in order to be first in line. OK so maybe they were trying to get into Apple’s WWDC that was on across the street, but there was still a buzz on the first morning as people queued up to get into DAC. Rumour has it that the difference between conferences is that DAC attendees are old enough to be the parents of a lot of WWDC attendees! However with age comes wisdom and experience and with that in mind there were plenty of learned souls milling around the exhibit halls!


2015-06-08 08.55.44.jpg

The first thing that has to be said is that the EDA industry is in rude health when a Google heavyweight is a speaker. Brian Otis was the man tasked with opening the conference proper this morning with his speech on the challenges facing IC design in relation to embedded biomedical devices. He has led the development of smart contact lenses that can constantly track biometric data and provide feedback on key points such as when a diabetic’s insulin levels are lower, and give a notification to the user via their smartphone (and not a shock or vibration, as I feared!). His talk made me realise that in order to deliver a revolutionary improvement such as this then it requires every stakeholder to look beyond their own specific area and focus on end use cases.  Of course, Google is fortunate enough to be big enough to make it happen with the help of its own partners and do this with contact lenses for example. On a hopeful note, the collaboration that takes place in SoC design means it can easily happen between companies in the EDA industry and IP design.


With Brian’s words in my head I walked around the show floor and realised very quickly why he chose to speak at this conference. There are vendors from all across the SoC spectrum; foundries, verification, RTL sign-off, software, IP, configuration tools, debug, validation, performance models and many more. Therefore this is the perfect opportunity to realise the vision of disruptive change through mass collaboration, when all of the stakeholders are together under the one roof.


Speaking of disruptive change, one of the highlights of the exhibit floor was seeing the Samsung Foundry booth with their 14nm silicon wafers as well as listening to the potential that 10nm can bring. We have all become used to numbers such as these but it is incredibly impressive to be able to mass-manufacture wafers at this size. A comparison to put things into perspective, airborne viruses such as the flu have a width profile four times the size of Samsung’s next generation manufacturing process!


2015-06-08 10.32.15.jpg

One of the big news items of the show so far has been the announcement that Synopsys are going to acquire Atrenta. Adding to the long list of acquisitions in the EDA industry, it got a lot of people talking on the first morning of the show. I stopped by the Atrenta booth to find out some more. Atrenta were more than happy about the news as they say it will “help to accelerate innovation across the SoC development community”. However I got more than I bargained for on the booth as the resident magician made my wristwatch vanish into thin air and reappear in the middle of a seemingly endless amount of locked boxes!


2015-06-08 12.30.59.jpg

Shout out to the Connected Community

There are a number of ARM Connected Community partners exhibiting at the show, each day I’ll bring you a short highlight of one partner. Today I got the chance to speak to Carbon’s  Jason Andrews.


We run performance models for hundreds of different IP configurations and SoC setups. Because we have over 10 years experience of doing this we are now able to make suggestions about what works best together depending on the IP customers are using and the PPA considerations they have. Another way that we work together with ARM is via our Swap and Play functionality that interacts with the Fast Models. Fast Models are really great because they work quickly, and what our tool does on top of that is allow users to stop the cycle at any time and get detailed analysis of a particular point they are interested in. Most system designers and architects know what area they are looking to optimise so it’s a case of providing them with the tools to really dive in deep and get precise information about what’s going on and how to maximise the performance.”

Soon after the men in the white coats came along to signify the beginning of Cocktail Hour on the show floor, and it was time to do some networking with a well-deserved beverage. Most people  tend to get engaged in deep and meaningful conversations over a beer or two, so the DAC organizers know their audience well

What's coming next in DAC day 2

I’ll be back tomorrow with my review of day 2 of DAC, here are the three events that I am most looking forward to:

  • Synopsys, Samsung and ARM collaborate to implement an ARM Cortex-A53 and CoreLink CCN-502 design on Samsung’s 14nm process at 7.30 tomorrow in Park Central Hotel.
  • Jeffrey Owens of Delphi Automotive gives a keynote on the innovations that will help design tomorrow’s automobiles in the Gateway Ballroom of the Moscone Center
  • Lip-Bu Tan, the CEO of Cadence, sits down at the DAC Pavilion to give a State of the Union address on the EDA industry, as well as answering your questions at booth 311
  • ARM’s William Orme, Cadence and Samsung all contribute to a ChipEstimate.com panel at 3pm to talk about next generation interconnect and IP tooling.

A little while ago, we announced the launch of our "Live Remote" training product. Using interactive webex technology, we are able to deliver any of our standard courses remotely, enabling ARM's instructors to reach a much wider audience than before.


In our efforts not to leave any stone unturned in ensuring that anyone who needs it can get access to the best ARM training on the market, we have partnered with MindShare  to start making selected parts of our training available in pre-recorded form so you can view them whenever and wherever you want. We’ve started with just a few courses but plan to continue releasing more to make up a library of content with something for everyone.


Check out what we’ve done so far at ARM Training Courses - ARM


If the course you want isn’t listed, please let us know what you are looking for and we’ll add it to the plan!



Chinese Version 中文版:通过智能配置进行系统汇编

The modern SoC is designed with many modular IP blocks that have been commercially licensed or reused from previous designs, along with some new proprietary components. Integrating all of the components has typically proven to be time-consuming and error-prone as designers stitch their SoCs together by hand or rigid and outdated scripts. Challenges also exist in the form of highly configurable IP blocks such as the interconnect fabric and debug & trace subsystem.


To address these issues ARM® launched three new tools today as part of an IP Tooling suite. They have been designed to solve challenges associated with SoC configurability and integration while reducing time to market with at least an 8x improvement in schedule.


The Socrates™ Design Environment (DE) is a complete tooling solution that handles the configuration and integration of ARM-based SoCs quickly and efficiently. It is through tooling that IP blocks can become greater than the sum of their parts, optimized for performance across the entire system.


There are also CoreSight™ Creator and CoreLink™ Creator, which are specialized tools that guide users through the configuration process of implementing a CoreSight debug and trace subsystem and CoreLink interconnect. The Creators focus specifically on these subsystems with many configurable pieces of IP that typically took months to configure and stitch currently.


The tools work together to enable ARM partners to configure and generate an SoC in days, not months. For example, the CoreSight Creator harvests data about the IP in the SoC, generates a CoreSight debug and trace subsystem description to match that is then fed back into the Socrates DE design flow, for integration into the overall SoC. When used together they deliver an integration experience that is seamless, from the configuration of individual components to the assembly of the SoC. The Creators use built-in ARM engineering intelligence to remove the need for expertise in the details of the CoreSight or CoreLink IP, allowing users to build integrate CoreSight and CoreLink IP in to their SoC with minimal engineering interaction.


All of the tools function by harvesting the IP-XACT description of each component in the system. The IP-XACT contains information on the registers, memory maps and interfaces, as well as master/slave relationships. The tools can effortlessly manage 100,000+ lines of connection meta-data per IP. Socrates DE then uses a simple rules-based methodology to capture design intent and automatically generate the connections. Whether it’s configuring a subsystem or the entire SoC, the Socrates tools work under the same premise. To give you an idea of how this can be achieved, let me take you through how it works using the example of a CoreSight subsystem.





Socrates tooling enables an intelligent system design flow

Historically you would have had to stitch together a CoreSight subsystem (such as the CoreSight SoC-400) manually using AMBA Designer or hand crafted top-level RTL. With CoreSight Creator you double click the menu item in the user interface, which launches the tool and begins harvesting the system information. This means it is reading all of the IP-XACT in the entire system design (for example, Cortex processors, System Trace Macrocell, interfaces).


It will identify the typical interfaces needed to describe and specify a CoreSight subsystem to generate a High Level Specification (HLS). The HLS defines the type of system interfaces from the System IP and processors that need to come into and out of a CoreSight debug and trace subsystem. CoreSight Creator will help create this HLS very quickly and seamlessly for users.





HLS for CoreSight Creator.png

High Level Specification of a CoreSight debug and trace subsystem




From there the tool can automatically run a Microarchitecture Synthesis and this will render out a microarchitecture of a CoreSight subsystem. The microarchitecture comprises the configuration specification of each CoreSight component and all interconnections to them. To do this today, system designers need to do it manually. This requires a very good understanding of the entire CoreSight catalog and CoreSight architecture.


With the schematic viewer on the user interface you can zoom in review the design by category: trace bus; debug access; timestamping; and cross-triggering. Even at that it is time-consuming and error-prone. The microarchitecture is rendered automatically so it removes the risk of error. For power users, the tool does permit manual editing of the microarchitecture so any capability, any configuration of the IP is available if required.





Socrates HLS.png

Schematic view of the Trace connections in CoreSight Creator





At each stage of the process there are multiple Design Rule Checks (DRC) that automatically check whether this is a valid microarchitecture and matches the HLS for the CoreSight subsystem. The DRCs clean the information and ensure the system is viable at each stage.






Socrates intelligent system design flow.png

Socrates tooling works together seamlessly to deliver an intelligent system design flow


CoreSight Creator system is sensitive to a change in information. If, for example, a newer version of the STM is introduced to the system all you have to do is re-harvest the IP-XACT and a new HLS is generated with the updated system information. This allows users to modify their design using an iterative loop that has had the time and pain removed from it. The potential for optimisation is significant as you can get the microarchitecture you desire.


When the iterative process for optimization is finished it is a simple task to generate deliverables. A click of a button is all it takes to build and generate the RTL, testbenches and test environments for the subsystem. It allows you to rapidly configure the system to match the actual target system elements. This info can be utilised back in the Socrates DE as the user interface is aware of all of the interfaces and HLS of the CoreSight subsystem and it just brings that to a SoC-wide level. There is no need for users to manually stitch the CoreSight to the rest of the system itself, it’s done automatically.


It not only creates CoreSight debug and trace – RTL, IP-XACT – but the example test environments as well There’s a lot of visualisation built into the tooling. For the HLS and microarchitecture there are schematics that show you what is happening at this stage. There is also a schematic for the RTL design.


At this stage the CoreSight debug and trace subsystem has been generated and is ready to be integrated with the rest of the SoC. The Socrates DE can now harvest the CoreSight information and use it as part of the greater system assembly process.




Guided IP Configuration.png

Insert ARM IP into your design at the click of a button with Socrates



Socrates DE features an IP Catalog that contains the IP-XACT information of all the ARM IP that a partner has licensed. It means that, for example, a partner can simply include any Cortex processor and CoreLink System IP into the system. While it is the best available tool for ARM IP, Socrates DE is vendor-agnostic, meaning it can handle any 3rd party and proprietary IP block by harvesting its IP-XACT description.





Configure a system with minimal engineering interaction

All of the IP Tooling provide real ARM integrated systems that are right first time. They intelligently integrate ARM IP, 3rd party IP and subsystems into the overall SoC with a methodology that dramatically reduces the design cycle. This saves time for system architects, allowing them to differentiate their SoC while maintaining design integrity.


With the release of the CoreSight Creator and CoreLink Creator, designers will no longer need extensive experience of the architecture to generate a debug subsystem or system interconnect that is optimized for their requirements. Its system intelligence makes it possible to configure an entire subsystem in a matter of days. By increasing the ease with which these highly configurable IP blocks are put together, it allows users to realise all of the performance advantages they contain. Previously, too often, available optimizations were overlooked due to time pressures to get the design taped out.


The IP tooling suite is being officially launched at DAC on June 8-10 at the Moscone Center in San Francisco. If you’re in the area then check out ARM at Booth #2428 to see live demonstrations of the tools. Find out more about the ARM presence at DAC.






Useful links for further information:

New ARM IP Tooling Suite Reduces SoC Integration Time from Months to Days

Whitepaper: IP-XACT Standardized IP Interfaces for Rapid IP Integration

Whitepaper: Solving Next Generation IP Configurability

Whitepaper: Lessons from the field – IP/SoC integration techniques that work

Socrates IP Tooling webpage

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