FFT feature in ProjectNe10
1 Introduction
Project Ne10 recently received an updated version of FFT, which is heavily NEON optimized for both ARM v7-A/v8-A AArch32 and v8-A AArch64 and is faster than almost all of the other existing open source FFT implementations such as FFTW and the FFT routine in OpenMax DL. This article will introduce this a bit.
2 Performance comparison with some other FFT’s on ARM v7-A
The following chart illustrates the benchmarking results of the complex FFT (32-bit float data type) of Ne10, FFTW and OpenMax. The test platform is ARM Cortex A9. The X-axis of the chart represents the length of FFT. The Y-axis represents the execution time of FFT. Smaller is better.
From this chart, we can find that Ne10 is better than FFTW, OpenMax DL in most of cases.
3 FFT on ARM v7-A/v8-A AArch32 and ARM v8-A AArch64
3.1 NEON usage
To utilize NEON accelerator, usually we have two choices:
- NEON assembly
- NEON intrinsic
The following table describes the pros and cons of using assembly/intrinsic.
| NEON assembly | NEON intrinsic |
Performance | Always shows the best performance for the specified platform | Depends heavily on the toolchain that is used |
Portability | The different ISA (i.e. ARM v7-A/v8-A AArch32 and ARM v8-A AArch64) has different assembly implementation. Even for the same ISA, the assembly might need to be fine-tuned to achieve ideal performance between different micro architectures. | Program once and run on different ISA’s. The compiler may also grant performance fine-tuning for different micro-architectures. |
Maintainability | Hard to read/write compared with C. | Similar to C code, it’s easy to read/write. |
3.2 ARM v7-A/v8-A AArch32 and v8-A AArch64 FFT implementations
According to the aforementioned pros/cons comparison, the intrinsic is preferred for the implementation of the Ne10 library
But for FFT, we still have different versions of implementations for ARM v7-A/v8-A AArch32 and v8-A AArch64 due to the reason described as follows:
// radix 4 butterfly with twiddles scratch[0].r = scratch_in[0].r; scratch[0].i = scratch_in[0].i; scratch[1].r = scratch_in[1].r * scratch_tw[0].r - scratch_in[1].i * scratch_tw[0].i; scratch[1].i = scratch_in[1].i * scratch_tw[0].r + scratch_in[1].r * scratch_tw[0].i; scratch[2].r = scratch_in[2].r * scratch_tw[1].r - scratch_in[2].i * scratch_tw[1].i; scratch[2].i = scratch_in[2].i * scratch_tw[1].r + scratch_in[2].r * scratch_tw[1].i; scratch[3].r = scratch_in[3].r * scratch_tw[2].r - scratch_in[3].i * scratch_tw[2].i; scratch[3].i = scratch_in[3].i * scratch_tw[2].r + scratch_in[3].r * scratch_tw[2].i; |
The above code snippet lists the basic element of FFT---- radix4 butterfly. From the code, we can conclude that:
- 20 64-bit NEON registers are needed if 2 radix4 butterflies are executed in one loop.
- 20 128-bit NEON registers are needed if 4 radix4 butterflies are executed in one loop.
And, for ARM v7-A/v8-A AArch32 and v8-A AArch64,
- There are 32 64-bit or 16 128-bit NEON registers for ARM v7-A/v8-A AArch32.
- There are 32 128-bit NEON registers for ARM v8-A AArch64.
Considering the above factors, in practice the implementation of Ne10 eventually has an assembly version, in which 2 radix4 butterflies are executed in one loop, for ARM v7-A/v8-A AAch32, and an intrinsic version, in which 4 radix4 butterflies are executed in one loop, for ARM v8-A AArch64.
3.3 C/NEON performance boost
The following charts show the C/NEON performance boosts in ARM v8-A AArch32 and AArch64 on the same Cortex-A53 CPU of Juno. Larger is better.
All the blue bars show the data in the AArch32 mode. The NEON code is v7-A/v8-A AArch32 assembly. The toolchain used is gcc 4.9.
All the red bars show the data in the AArch64 mode. The NEON code is intrinsic. The performance of intrinsic depends on toolchains greatly. The toolchain used here is llvm3.5.
From these charts, we can conclude that float complex FFT shows the similar or better performance boost between the AArch64 mode and the AArch32 mode. But for int32/16 complex FFT, the performance boost in the AArch32 mode is usually better than in the AArch64 mode (but this doesn’t mean the int32/16 complex FFT performs faster in the AArch32 mode than in the AArch64 mode!)
The data from this exercise is useful to analyze the performance boost for ARM v8-A AArch64 mode but we still need more data to verify and reinforce our concept.
3.4 AArch32/AArch64 performance boost
The following charts are based on performance of the AArch32 C version and show the performance ratios of the AArch32 NEON version and the AArch64 C version, and the AArch64 NEON version on the same Cortex-A53 CPU on Juno. Larger is better.
From these charts, we can conclude that FFT in the AArch64 mode performs faster than in the AArch32 mode, no matter C or NEON.
4 Usage
4.1 APIs
The FFT still supports the following features:
Feature | Data type | Length |
c2c FFT/IFFT | float/int32/int16 | 2^N (N is 2, 3….) |
r2c FFT | float/int32/int16 | 2^N (N is 3, 4….) |
c2r IFFT | float/int32/int16 | 2^N (N is 3, 4….) |
But the APIs have changed. The old users need to update to latest version v1.1.2 or master.
More API details, please check http://projectne10.github.io/Ne10/doc/group__C2C__FFT__IFFT.html.
4.2 Example
Take the float c2c FFT/IFFT as an example, current APIs are used as follows.
#include "NE10.h" …… { fftSize = 2^N; //N is 2, 3, 4, 5, 6.... in = (ne10_fft_cpx_float32_t*) NE10_MALLOC (fftSize * sizeof (ne10_fft_cpx_float32_t)); out = (ne10_fft_cpx_float32_t*) NE10_MALLOC (fftSize * sizeof (ne10_fft_cpx_float32_t)); ne10_fft_cfg_float32_t cfg; cfg = ne10_fft_alloc_c2c_float32 (fftSize); …… //FFT ne10_fft_c2c_1d_float32_neon (out, in, cfg, 0); …… //IFFT ne10_fft_c2c_1d_float32_neon (out, in, cfg, 1); …… NE10_FREE (in); NE10_FREE (out); NE10_FREE (cfg); } |
5 Conclusion
The FFT shows that you can get a significant performance boost in the ARM v8-A AArch64 mode. You may find more use cases of course. We welcome feedback and are looking to publish use cases to cross promote ProjectNe10 and the projects that use it.
For more details, please access http://projectne10.github.com/Ne10/
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