Calypto® Design Systems’ family of products enables SoC and FPGA
designers to quickly create fully-verified, power-optimized RTL
for downstream synthesis and physical implementation.
Catapult High Level Design
& Verification Platform
|PowerPro RTL Low Power Platform|
Catapult is the only high level synthesis tool supporting both C++ and SystemC. From these high level descriptions, Catapult automatically generates production-quality and verification-ready RTL. This dramatically shortens both design and verification time. Catapult LP utilized advanced low power techniques to synthesize power-optimized RTL. SLEC uses formal methods to comprehensively prove equivalence between the SystemC or C++ input against the synthesized RTL output.
|PowerPro is a family of products for low power RTL design that includes physically-aware power analysis and automated RTL power optimization. It utilizes deep sequential analysis to identify and insert low power logic into the RTL for maximum power savings. It supports automatic and guided flows, and has been demonstrated to reduce power by up to 60% across a variety of complex designs. SLEC Pro automatically verifies that the low power RTL output of PowerPro is functionally equivalent to the original RTL source.|
|SLEC Family Datasheet 11 months ago||by mathildekarsenti|
|PowerPro Family Datasheet 11 months ago||by mathildekarsenti|
|Catapult Family Datasheet 11 months ago||by mathildekarsenti|
|PowerPro MG - Calypto Design Systems 11 months ago||by mathildekarsenti|
|SLEC RTL - Calypto Design Systems 11 months ago||by mathildekarsenti|
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