Blue Pearl Software focuses on solving the RTL analysis challenges designers face. Its Blue Pearl Software Suite offers automatically generated Synopsys Design Constraints (SDCs), offers lint and clock domain crossing (CDC) checking and a Visual Verification Environment. These capabilities reduce the number of iterations required to close timing of multi-language (VHDL, Verilog, SystemVerilog) designs. The software runs natively on Windows and Linux platforms, and is used for FPGA, ASIC and SOC designs.
|Suit up to ACE Your Clock Domain Crossing (CDC) Analysis for Free 12 months ago||by shakeeljeeawoody|
|Improve Quality of Results (QoR) with Grey Cell™ Methodology 2 years ago||by shakeeljeeawoody|
|Application Note: Automatic Multi Cycle Path Detection from RTL 2 years ago||by shakeeljeeawoody|
|Blue Pearl Software Suite Datasheet 2 years ago||by shakeeljeeawoody|
|Blue Pearl Software Suite by Blue Pearl Software 2 years ago||by shakeeljeeawoody|
You can't create discussions here, but as discussions appear they might have answers you need.
As soon as people join and begin creating and sharing content, you'll begin seeing activity here. Create something now to get started!